Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	164586711	5231075	0	0
clk_enables_rd_A	164586711	52533	0	0
clk_hints_rd_A	164586711	47144	0	0
extclk_ctrl_rd_A	164586711	59038	0	0
extclk_ctrl_regwen_rd_A	164586711	44901	0	0
jitter_enable_rd_A	164586711	63889	0	0
jitter_regwen_rd_A	164586711	50686	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	5231075	0	0
T2	549804	267233	0	0
T3	494226	143070	0	0
T12	0	156583	0	0
T14	0	127336	0	0
T16	0	53919	0	0
T26	0	131481	0	0
T27	0	49675	0	0
T28	1212	0	0	0
T29	1235	0	0	0
T30	1530	0	0	0
T31	23781	0	0	0
T32	1419	0	0	0
T33	113302	0	0	0
T38	1999	0	0	0
T39	2717	0	0	0
T76	0	160728	0	0
T77	0	63982	0	0
T78	0	72889	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	52533	0	0
T1	205499	0	0	0
T3	0	5536	0	0
T4	26910	0	0	0
T5	37628	4	0	0
T6	1054	0	0	0
T7	1720	0	0	0
T14	0	2543	0	0
T16	0	2171	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T25	2427	0	0	0
T27	0	1743	0	0
T61	0	6	0	0
T77	0	1573	0	0
T78	0	1535	0	0
T129	0	2	0	0
T130	0	9	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	47144	0	0
T1	205499	0	0	0
T3	0	5149	0	0
T4	26910	0	0	0
T5	37628	6	0	0
T6	1054	0	0	0
T7	1720	0	0	0
T14	0	2313	0	0
T16	0	1995	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T25	2427	0	0	0
T27	0	1570	0	0
T61	0	9	0	0
T77	0	1218	0	0
T78	0	1257	0	0
T112	0	3	0	0
T130	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	59038	0	0
T1	205499	0	0	0
T3	0	6004	0	0
T4	26910	120	0	0
T5	37628	12	0	0
T6	1054	0	0	0
T7	1720	9	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T22	0	44	0	0
T25	2427	0	0	0
T39	0	70	0	0
T89	0	18	0	0
T131	0	74	0	0
T132	0	53	0	0
T133	0	15	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	44901	0	0
T2	549804	0	0	0
T3	494226	4815	0	0
T4	26910	40	0	0
T14	0	2363	0	0
T16	0	1967	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0
T27	0	1722	0	0
T28	1212	0	0	0
T46	7084	0	0	0
T134	0	50	0	0
T135	0	11	0	0
T136	0	45	0	0
T137	0	6	0	0
T138	0	33	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	63889	0	0
T1	205499	0	0	0
T3	0	6497	0	0
T4	26910	0	0	0
T5	37628	98	0	0
T6	1054	0	0	0
T7	1720	0	0	0
T14	0	2847	0	0
T16	0	3039	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T25	2427	0	0	0
T27	0	2243	0	0
T61	0	74	0	0
T77	0	1926	0	0
T112	0	47	0	0
T129	0	149	0	0
T139	0	67	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164586711	50686	0	0
T3	494226	5792	0	0
T14	0	2578	0	0
T16	0	2167	0	0
T27	0	1772	0	0
T29	1235	0	0	0
T30	1530	0	0	0
T31	23781	0	0	0
T32	1419	0	0	0
T33	113302	0	0	0
T38	1999	0	0	0
T39	2717	0	0	0
T41	1993	0	0	0
T42	0	3298	0	0
T77	0	1235	0	0
T78	0	1512	0	0
T109	2811	0	0	0
T140	0	1516	0	0
T141	0	4043	0	0
T142	0	1980	0	0