Module Definition
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Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_div2_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_div4_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_main_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_usb_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
79.17 94.00 85.71 86.96 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T6,T7

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2147483647 15691682 0 0
SyncReqAckHoldReq 2147483647 136074 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 15691682 0 0
T1 307116 110 0 0
T2 549804 109 0 0
T3 494226 99 0 0
T4 69885 30 0 0
T5 78406 482 0 0
T6 876 29 0 0
T7 1771 52 0 0
T10 0 7 0 0
T11 0 8 0 0
T12 0 178 0 0
T13 0 24 0 0
T14 0 85 0 0
T15 0 12 0 0
T16 0 99 0 0
T17 4661 98 0 0
T18 3887 81 0 0
T19 3181 54 0 0
T20 4464 111 0 0
T21 1057 0 0 0
T22 1687 0 0 0
T23 30697 0 0 0
T24 1762 0 0 0
T25 1222 38 0 0
T26 0 93 0 0
T27 0 39 0 0
T28 1212 0 0 0
T29 1235 0 0 0
T30 1530 0 0 0
T31 23781 0 0 0
T32 1419 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 136074 0 0
T1 618451 205 0 0
T2 130293 3004 0 0
T3 214714 2234 0 0
T4 349668 150 0 0
T5 78406 160 0 0
T10 0 10 0 0
T11 0 22 0 0
T12 0 288 0 0
T13 0 58 0 0
T14 0 175 0 0
T15 0 43 0 0
T16 0 175 0 0
T17 18989 0 0 0
T18 15658 0 0 0
T19 10233 0 0 0
T20 21052 0 0 0
T21 17264 0 0 0
T22 17727 0 0 0
T23 126868 50 0 0
T24 61410 0 0 0
T26 0 115 0 0
T27 0 39 0 0
T28 660 0 0 0
T29 1255 0 0 0
T30 1548 0 0 0
T31 19048 80 0 0
T32 949 0 0 0
T33 15583 149 0 0
T34 0 10 0 0
T35 0 80 0 0
T36 0 4 0 0
T37 0 11 0 0
T38 470 0 0 0
T39 707 0 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 415561848 3137127 0 0
SyncReqAckHoldReq 14166431 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 415561848 3137127 0 0
T1 203368 96 0 0
T4 129165 30 0 0
T5 156647 482 0 0
T6 1886 30 0 0
T7 3304 52 0 0
T17 6269 99 0 0
T18 5183 81 0 0
T19 3377 54 0 0
T20 6946 112 0 0
T25 2402 38 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 14166431 0 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 206936213 3136995 0 0
SyncReqAckHoldReq 14166431 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936213 3136995 0 0
T1 101617 96 0 0
T4 42975 30 0 0
T5 78406 482 0 0
T6 876 29 0 0
T7 1771 52 0 0
T17 3095 98 0 0
T18 2538 81 0 0
T19 1669 54 0 0
T20 3447 111 0 0
T25 1222 38 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 14166431 0 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 103467486 2993547 0 0
SyncReqAckHoldReq 14166431 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 103467486 2993547 0 0
T1 50809 96 0 0
T4 21486 30 0 0
T5 39202 461 0 0
T6 438 26 0 0
T7 885 51 0 0
T17 1547 93 0 0
T18 1269 77 0 0
T19 835 51 0 0
T20 1723 106 0 0
T25 610 36 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 14166431 0 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 443046840 3141037 0 0
SyncReqAckHoldReq 14166431 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 443046840 3141037 0 0
T1 211849 96 0 0
T4 134553 30 0 0
T5 229179 509 0 0
T6 1784 27 0 0
T7 3442 52 0 0
T17 6530 99 0 0
T18 5399 81 0 0
T19 3518 54 0 0
T20 7212 110 0 0
T25 2502 38 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 14166431 0 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T5,T6,T7
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 212569675 3140897 0 0
SyncReqAckHoldReq 14166431 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 212569675 3140897 0 0
T1 101689 96 0 0
T4 64585 30 0 0
T5 110007 509 0 0
T6 944 30 0 0
T7 1652 52 0 0
T17 3134 98 0 0
T18 2592 81 0 0
T19 1688 54 0 0
T20 3408 108 0 0
T25 1201 38 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 14166431 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T1,T4
11CoveredT5,T1,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 164586711 25677 0 0
SyncReqAckHoldReq 418764508 24496 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 164586711 25677 0 0
T1 205499 41 0 0
T2 0 577 0 0
T3 0 450 0 0
T4 26910 32 0 0
T5 37628 32 0 0
T6 1054 0 0 0
T7 1720 0 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T23 0 10 0 0
T25 2427 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 418764508 24496 0 0
T1 203368 36 0 0
T2 0 556 0 0
T3 0 409 0 0
T4 129165 32 0 0
T5 156647 32 0 0
T6 1886 0 0 0
T7 3304 0 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3377 0 0 0
T20 6946 0 0 0
T23 0 10 0 0
T25 2402 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T1,T4
11CoveredT5,T1,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 164586711 25677 0 0
SyncReqAckHoldReq 208492531 24495 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 164586711 25677 0 0
T1 205499 41 0 0
T2 0 577 0 0
T3 0 450 0 0
T4 26910 32 0 0
T5 37628 32 0 0
T6 1054 0 0 0
T7 1720 0 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T23 0 10 0 0
T25 2427 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 208492531 24495 0 0
T1 101617 36 0 0
T2 0 556 0 0
T3 0 409 0 0
T4 42975 32 0 0
T5 78406 32 0 0
T6 876 0 0 0
T7 1771 0 0 0
T17 3095 0 0 0
T18 2538 0 0 0
T19 1669 0 0 0
T20 3447 0 0 0
T23 0 10 0 0
T25 1222 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T1,T4
11CoveredT5,T1,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 164586711 25677 0 0
SyncReqAckHoldReq 104245656 24471 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 164586711 25677 0 0
T1 205499 41 0 0
T2 0 577 0 0
T3 0 450 0 0
T4 26910 32 0 0
T5 37628 32 0 0
T6 1054 0 0 0
T7 1720 0 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T23 0 10 0 0
T25 2427 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 104245656 24471 0 0
T1 50809 36 0 0
T2 0 556 0 0
T3 0 409 0 0
T4 21486 32 0 0
T5 39202 32 0 0
T6 438 0 0 0
T7 885 0 0 0
T17 1547 0 0 0
T18 1269 0 0 0
T19 835 0 0 0
T20 1723 0 0 0
T23 0 10 0 0
T25 610 0 0 0
T31 0 16 0 0
T33 0 35 0 0
T34 0 2 0 0
T35 0 17 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T1,T4
11CoveredT5,T1,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 164586711 25677 0 0
SyncReqAckHoldReq 446383079 24496 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 164586711 25677 0 0
T1 205499 41 0 0
T2 0 577 0 0
T3 0 450 0 0
T4 26910 32 0 0
T5 37628 32 0 0
T6 1054 0 0 0
T7 1720 0 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T23 0 10 0 0
T25 2427 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 446383079 24496 0 0
T1 211849 36 0 0
T2 0 556 0 0
T3 0 409 0 0
T4 134553 32 0 0
T5 229179 32 0 0
T6 1784 0 0 0
T7 3442 0 0 0
T17 6530 0 0 0
T18 5399 0 0 0
T19 3518 0 0 0
T20 7212 0 0 0
T23 0 10 0 0
T25 2502 0 0 0
T31 0 16 0 0
T33 0 38 0 0
T34 0 2 0 0
T35 0 18 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T1,T4
11CoveredT5,T1,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT5,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T1,T4
EVEN 0 - Covered T5,T1,T4
ODD - 1 Covered T5,T1,T4
ODD - 0 Covered T5,T1,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 164586711 25187 0 0
SyncReqAckHoldReq 214171043 23932 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 164586711 25187 0 0
T1 205499 41 0 0
T2 0 577 0 0
T3 0 450 0 0
T4 26910 24 0 0
T5 37628 32 0 0
T6 1054 0 0 0
T7 1720 0 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T23 0 10 0 0
T25 2427 0 0 0
T31 0 16 0 0
T33 0 19 0 0
T34 0 2 0 0
T35 0 9 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 214171043 23932 0 0
T1 101689 36 0 0
T2 0 556 0 0
T3 0 409 0 0
T4 64585 22 0 0
T5 110007 32 0 0
T6 944 0 0 0
T7 1652 0 0 0
T17 3134 0 0 0
T18 2592 0 0 0
T19 1688 0 0 0
T20 3408 0 0 0
T23 0 10 0 0
T25 1201 0 0 0
T31 0 16 0 0
T34 0 2 0 0
T35 0 9 0 0
T36 0 4 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 163702864 2805 0 0
SyncReqAckHoldReq 415561848 2805 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 163702864 2805 0 0
T1 205499 7 0 0
T2 0 56 0 0
T3 0 34 0 0
T4 26910 0 0 0
T11 0 4 0 0
T12 0 71 0 0
T13 0 23 0 0
T14 0 41 0 0
T15 0 9 0 0
T16 0 49 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T21 1057 0 0 0
T22 1687 0 0 0
T23 30697 0 0 0
T24 1762 0 0 0
T26 0 22 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 415561848 2805 0 0
T1 203368 7 0 0
T2 0 56 0 0
T3 0 34 0 0
T4 129165 0 0 0
T11 0 4 0 0
T12 0 71 0 0
T13 0 23 0 0
T14 0 41 0 0
T15 0 9 0 0
T16 0 49 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3377 0 0 0
T20 6946 0 0 0
T21 6770 0 0 0
T22 6753 0 0 0
T23 42859 0 0 0
T24 24166 0 0 0
T26 0 22 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 163702864 2951 0 0
SyncReqAckHoldReq 206936213 2951 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 163702864 2951 0 0
T1 205499 14 0 0
T2 0 68 0 0
T3 0 43 0 0
T4 26910 0 0 0
T10 0 7 0 0
T12 0 82 0 0
T13 0 5 0 0
T14 0 50 0 0
T15 0 12 0 0
T16 0 48 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T21 1057 0 0 0
T22 1687 0 0 0
T23 30697 0 0 0
T24 1762 0 0 0
T26 0 41 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936213 2951 0 0
T1 101617 14 0 0
T2 0 68 0 0
T3 0 43 0 0
T4 42975 0 0 0
T10 0 7 0 0
T12 0 82 0 0
T13 0 5 0 0
T14 0 50 0 0
T15 0 12 0 0
T16 0 48 0 0
T17 3095 0 0 0
T18 2538 0 0 0
T19 1669 0 0 0
T20 3447 0 0 0
T21 3442 0 0 0
T22 3939 0 0 0
T23 21363 0 0 0
T24 12071 0 0 0
T26 0 41 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T11
11CoveredT2,T3,T11

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT2,T3,T11

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T2,T3,T11
EVEN 0 - Covered T2,T3,T11
ODD - 1 Covered T2,T3,T11
ODD - 0 Covered T2,T3,T11


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T2,T3,T11
EVEN 0 - Covered T2,T3,T11
ODD - 1 Covered T2,T3,T11
ODD - 0 Covered T2,T3,T11


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 163702864 2819 0 0
SyncReqAckHoldReq 103467486 2819 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 163702864 2819 0 0
T2 549804 41 0 0
T3 494226 56 0 0
T11 0 8 0 0
T12 0 96 0 0
T13 0 19 0 0
T14 0 35 0 0
T16 0 51 0 0
T26 0 52 0 0
T27 0 39 0 0
T28 1212 0 0 0
T29 1235 0 0 0
T30 1530 0 0 0
T31 23781 0 0 0
T32 1419 0 0 0
T33 113302 0 0 0
T37 0 11 0 0
T38 1999 0 0 0
T39 2717 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 103467486 2819 0 0
T2 130293 41 0 0
T3 214714 56 0 0
T11 0 8 0 0
T12 0 96 0 0
T13 0 19 0 0
T14 0 35 0 0
T16 0 51 0 0
T26 0 52 0 0
T27 0 39 0 0
T28 660 0 0 0
T29 1255 0 0 0
T30 1548 0 0 0
T31 19048 0 0 0
T32 949 0 0 0
T33 15583 0 0 0
T37 0 11 0 0
T38 470 0 0 0
T39 707 0 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 163702864 2987 0 0
SyncReqAckHoldReq 443046840 2987 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 163702864 2987 0 0
T1 205499 4 0 0
T2 0 59 0 0
T3 0 56 0 0
T4 26910 0 0 0
T10 0 3 0 0
T11 0 10 0 0
T12 0 39 0 0
T13 0 11 0 0
T14 0 49 0 0
T15 0 22 0 0
T16 0 27 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T21 1057 0 0 0
T22 1687 0 0 0
T23 30697 0 0 0
T24 1762 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 443046840 2987 0 0
T1 211849 4 0 0
T2 0 59 0 0
T3 0 56 0 0
T4 134553 0 0 0
T10 0 3 0 0
T11 0 10 0 0
T12 0 39 0 0
T13 0 11 0 0
T14 0 49 0 0
T15 0 22 0 0
T16 0 27 0 0
T17 6530 0 0 0
T18 5399 0 0 0
T19 3518 0 0 0
T20 7212 0 0 0
T21 7052 0 0 0
T22 7035 0 0 0
T23 62646 0 0 0
T24 25173 0 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 163702864 2622 0 0
SyncReqAckHoldReq 212569675 2622 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 163702864 2622 0 0
T1 205499 12 0 0
T2 0 39 0 0
T3 0 43 0 0
T4 26910 0 0 0
T11 0 11 0 0
T12 0 83 0 0
T13 0 16 0 0
T14 0 37 0 0
T16 0 38 0 0
T17 1566 0 0 0
T18 1349 0 0 0
T19 1512 0 0 0
T20 1017 0 0 0
T21 1057 0 0 0
T22 1687 0 0 0
T23 30697 0 0 0
T24 1762 0 0 0
T26 0 49 0 0
T40 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 212569675 2622 0 0
T1 101689 12 0 0
T2 0 39 0 0
T3 0 43 0 0
T4 64585 0 0 0
T11 0 11 0 0
T12 0 83 0 0
T13 0 16 0 0
T14 0 37 0 0
T16 0 38 0 0
T17 3134 0 0 0
T18 2592 0 0 0
T19 1688 0 0 0
T20 3408 0 0 0
T21 3385 0 0 0
T22 3376 0 0 0
T23 27190 0 0 0
T24 12083 0 0 0
T26 0 49 0 0
T40 0 12 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%