Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T7,T25
10CoveredT5,T7,T25
11CoveredT5,T7,T25

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 415562283 4523 0 0
g_div2.Div2Whole_A 415562283 5296 0 0
g_div4.Div4Stepped_A 206936636 4432 0 0
g_div4.Div4Whole_A 206936636 5015 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415562283 4523 0 0
T1 203368 0 0 0
T2 0 45 0 0
T3 0 84 0 0
T4 129166 0 0 0
T5 156647 3 0 0
T6 1887 0 0 0
T7 3304 4 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3378 0 0 0
T20 6946 0 0 0
T21 0 1 0 0
T22 0 9 0 0
T25 2402 0 0 0
T29 0 4 0 0
T30 0 7 0 0
T32 0 2 0 0
T46 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415562283 5296 0 0
T1 203368 0 0 0
T2 0 59 0 0
T3 0 94 0 0
T4 129166 0 0 0
T5 156647 4 0 0
T6 1887 0 0 0
T7 3304 6 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3378 0 0 0
T20 6946 0 0 0
T21 0 1 0 0
T22 0 10 0 0
T25 2402 6 0 0
T29 0 4 0 0
T30 0 7 0 0
T46 0 4 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936636 4432 0 0
T1 101618 0 0 0
T2 0 41 0 0
T3 0 83 0 0
T4 42975 0 0 0
T5 78407 3 0 0
T6 876 0 0 0
T7 1772 4 0 0
T17 3095 0 0 0
T18 2539 0 0 0
T19 1670 0 0 0
T20 3447 0 0 0
T21 0 1 0 0
T22 0 9 0 0
T25 1222 0 0 0
T29 0 4 0 0
T30 0 7 0 0
T32 0 2 0 0
T46 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936636 5015 0 0
T1 101618 0 0 0
T2 0 44 0 0
T3 0 94 0 0
T4 42975 0 0 0
T5 78407 4 0 0
T6 876 0 0 0
T7 1772 6 0 0
T17 3095 0 0 0
T18 2539 0 0 0
T19 1670 0 0 0
T20 3447 0 0 0
T21 0 1 0 0
T22 0 10 0 0
T25 1222 6 0 0
T29 0 4 0 0
T30 0 7 0 0
T46 0 4 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T7,T25
10CoveredT5,T7,T25
11CoveredT5,T7,T25

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 415562283 4523 0 0
g_div2.Div2Whole_A 415562283 5296 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415562283 4523 0 0
T1 203368 0 0 0
T2 0 45 0 0
T3 0 84 0 0
T4 129166 0 0 0
T5 156647 3 0 0
T6 1887 0 0 0
T7 3304 4 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3378 0 0 0
T20 6946 0 0 0
T21 0 1 0 0
T22 0 9 0 0
T25 2402 0 0 0
T29 0 4 0 0
T30 0 7 0 0
T32 0 2 0 0
T46 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415562283 5296 0 0
T1 203368 0 0 0
T2 0 59 0 0
T3 0 94 0 0
T4 129166 0 0 0
T5 156647 4 0 0
T6 1887 0 0 0
T7 3304 6 0 0
T17 6269 0 0 0
T18 5183 0 0 0
T19 3378 0 0 0
T20 6946 0 0 0
T21 0 1 0 0
T22 0 10 0 0
T25 2402 6 0 0
T29 0 4 0 0
T30 0 7 0 0
T46 0 4 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T7,T25
10CoveredT5,T7,T25
11CoveredT5,T7,T25

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 206936636 4432 0 0
g_div4.Div4Whole_A 206936636 5015 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936636 4432 0 0
T1 101618 0 0 0
T2 0 41 0 0
T3 0 83 0 0
T4 42975 0 0 0
T5 78407 3 0 0
T6 876 0 0 0
T7 1772 4 0 0
T17 3095 0 0 0
T18 2539 0 0 0
T19 1670 0 0 0
T20 3447 0 0 0
T21 0 1 0 0
T22 0 9 0 0
T25 1222 0 0 0
T29 0 4 0 0
T30 0 7 0 0
T32 0 2 0 0
T46 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 206936636 5015 0 0
T1 101618 0 0 0
T2 0 44 0 0
T3 0 94 0 0
T4 42975 0 0 0
T5 78407 4 0 0
T6 876 0 0 0
T7 1772 6 0 0
T17 3095 0 0 0
T18 2539 0 0 0
T19 1670 0 0 0
T20 3447 0 0 0
T21 0 1 0 0
T22 0 10 0 0
T25 1222 6 0 0
T29 0 4 0 0
T30 0 7 0 0
T46 0 4 0 0

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