SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T7,T25 |
1 | 0 | Covered | T5,T7,T25 |
1 | 1 | Covered | T5,T7,T25 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 415562283 | 4523 | 0 | 0 |
g_div2.Div2Whole_A | 415562283 | 5296 | 0 | 0 |
g_div4.Div4Stepped_A | 206936636 | 4432 | 0 | 0 |
g_div4.Div4Whole_A | 206936636 | 5015 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415562283 | 4523 | 0 | 0 |
T1 | 203368 | 0 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T3 | 0 | 84 | 0 | 0 |
T4 | 129166 | 0 | 0 | 0 |
T5 | 156647 | 3 | 0 | 0 |
T6 | 1887 | 0 | 0 | 0 |
T7 | 3304 | 4 | 0 | 0 |
T17 | 6269 | 0 | 0 | 0 |
T18 | 5183 | 0 | 0 | 0 |
T19 | 3378 | 0 | 0 | 0 |
T20 | 6946 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T25 | 2402 | 0 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T32 | 0 | 2 | 0 | 0 |
T46 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415562283 | 5296 | 0 | 0 |
T1 | 203368 | 0 | 0 | 0 |
T2 | 0 | 59 | 0 | 0 |
T3 | 0 | 94 | 0 | 0 |
T4 | 129166 | 0 | 0 | 0 |
T5 | 156647 | 4 | 0 | 0 |
T6 | 1887 | 0 | 0 | 0 |
T7 | 3304 | 6 | 0 | 0 |
T17 | 6269 | 0 | 0 | 0 |
T18 | 5183 | 0 | 0 | 0 |
T19 | 3378 | 0 | 0 | 0 |
T20 | 6946 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2402 | 6 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T46 | 0 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 206936636 | 4432 | 0 | 0 |
T1 | 101618 | 0 | 0 | 0 |
T2 | 0 | 41 | 0 | 0 |
T3 | 0 | 83 | 0 | 0 |
T4 | 42975 | 0 | 0 | 0 |
T5 | 78407 | 3 | 0 | 0 |
T6 | 876 | 0 | 0 | 0 |
T7 | 1772 | 4 | 0 | 0 |
T17 | 3095 | 0 | 0 | 0 |
T18 | 2539 | 0 | 0 | 0 |
T19 | 1670 | 0 | 0 | 0 |
T20 | 3447 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T25 | 1222 | 0 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T32 | 0 | 2 | 0 | 0 |
T46 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 206936636 | 5015 | 0 | 0 |
T1 | 101618 | 0 | 0 | 0 |
T2 | 0 | 44 | 0 | 0 |
T3 | 0 | 94 | 0 | 0 |
T4 | 42975 | 0 | 0 | 0 |
T5 | 78407 | 4 | 0 | 0 |
T6 | 876 | 0 | 0 | 0 |
T7 | 1772 | 6 | 0 | 0 |
T17 | 3095 | 0 | 0 | 0 |
T18 | 2539 | 0 | 0 | 0 |
T19 | 1670 | 0 | 0 | 0 |
T20 | 3447 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1222 | 6 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T46 | 0 | 4 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T7,T25 |
1 | 0 | Covered | T5,T7,T25 |
1 | 1 | Covered | T5,T7,T25 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 415562283 | 4523 | 0 | 0 |
g_div2.Div2Whole_A | 415562283 | 5296 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415562283 | 4523 | 0 | 0 |
T1 | 203368 | 0 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T3 | 0 | 84 | 0 | 0 |
T4 | 129166 | 0 | 0 | 0 |
T5 | 156647 | 3 | 0 | 0 |
T6 | 1887 | 0 | 0 | 0 |
T7 | 3304 | 4 | 0 | 0 |
T17 | 6269 | 0 | 0 | 0 |
T18 | 5183 | 0 | 0 | 0 |
T19 | 3378 | 0 | 0 | 0 |
T20 | 6946 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T25 | 2402 | 0 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T32 | 0 | 2 | 0 | 0 |
T46 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415562283 | 5296 | 0 | 0 |
T1 | 203368 | 0 | 0 | 0 |
T2 | 0 | 59 | 0 | 0 |
T3 | 0 | 94 | 0 | 0 |
T4 | 129166 | 0 | 0 | 0 |
T5 | 156647 | 4 | 0 | 0 |
T6 | 1887 | 0 | 0 | 0 |
T7 | 3304 | 6 | 0 | 0 |
T17 | 6269 | 0 | 0 | 0 |
T18 | 5183 | 0 | 0 | 0 |
T19 | 3378 | 0 | 0 | 0 |
T20 | 6946 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2402 | 6 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T46 | 0 | 4 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T7,T25 |
1 | 0 | Covered | T5,T7,T25 |
1 | 1 | Covered | T5,T7,T25 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 206936636 | 4432 | 0 | 0 |
g_div4.Div4Whole_A | 206936636 | 5015 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 206936636 | 4432 | 0 | 0 |
T1 | 101618 | 0 | 0 | 0 |
T2 | 0 | 41 | 0 | 0 |
T3 | 0 | 83 | 0 | 0 |
T4 | 42975 | 0 | 0 | 0 |
T5 | 78407 | 3 | 0 | 0 |
T6 | 876 | 0 | 0 | 0 |
T7 | 1772 | 4 | 0 | 0 |
T17 | 3095 | 0 | 0 | 0 |
T18 | 2539 | 0 | 0 | 0 |
T19 | 1670 | 0 | 0 | 0 |
T20 | 3447 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T25 | 1222 | 0 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T32 | 0 | 2 | 0 | 0 |
T46 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 206936636 | 5015 | 0 | 0 |
T1 | 101618 | 0 | 0 | 0 |
T2 | 0 | 44 | 0 | 0 |
T3 | 0 | 94 | 0 | 0 |
T4 | 42975 | 0 | 0 | 0 |
T5 | 78407 | 4 | 0 | 0 |
T6 | 876 | 0 | 0 | 0 |
T7 | 1772 | 6 | 0 | 0 |
T17 | 3095 | 0 | 0 | 0 |
T18 | 2539 | 0 | 0 | 0 |
T19 | 1670 | 0 | 0 | 0 |
T20 | 3447 | 0 | 0 | 0 |
T21 | 0 | 1 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1222 | 6 | 0 | 0 |
T29 | 0 | 4 | 0 | 0 |
T30 | 0 | 7 | 0 | 0 |
T46 | 0 | 4 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |