Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	491108592	397	0	0
StatusRise_A	491108592	397	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491108592	397	0	0
T1	616497	0	0	0
T4	80730	0	0	0
T6	3162	10	0	0
T7	5160	0	0	0
T17	4698	0	0	0
T18	4047	0	0	0
T19	4536	0	0	0
T20	3051	8	0	0
T21	3171	0	0	0
T25	7281	0	0	0
T45	0	10	0	0
T143	0	9	0	0
T144	0	9	0	0
T145	0	5	0	0
T146	0	2	0	0
T147	0	13	0	0
T148	0	13	0	0
T149	0	8	0	0
T150	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491108592	397	0	0
T1	616497	0	0	0
T4	80730	0	0	0
T6	3162	10	0	0
T7	5160	0	0	0
T17	4698	0	0	0
T18	4047	0	0	0
T19	4536	0	0	0
T20	3051	8	0	0
T21	3171	0	0	0
T25	7281	0	0	0
T45	0	10	0	0
T143	0	9	0	0
T144	0	9	0	0
T145	0	5	0	0
T146	0	2	0	0
T147	0	13	0	0
T148	0	13	0	0
T149	0	8	0	0
T150	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163702864	130	0	0
StatusRise_A	163702864	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	130	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	3	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	2	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	130	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	3	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	2	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163702864	132	0	0
StatusRise_A	163702864	132	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	132	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	3	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	3	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	132	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	3	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	3	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163702864	135	0	0
StatusRise_A	163702864	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	135	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	4	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	3	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	3	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	135	0	0
T1	205499	0	0	0
T4	26910	0	0	0
T6	1054	4	0	0
T7	1720	0	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	3	0	0
T21	1057	0	0	0
T25	2427	0	0	0
T45	0	3	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	1	0	0