Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46719	0	0
CgEnOn_A	2147483647	37286	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46719	0	0
T1	2287678	3	0	0
T2	0	66	0	0
T4	1366712	51	0	0
T5	1300978	48	0	0
T6	19868	30	0	0
T7	37646	3	0	0
T17	70364	3	0	0
T18	58096	6	0	0
T19	37916	6	0	0
T20	77766	29	0	0
T21	32864	0	0	0
T24	0	7	0	0
T25	27102	3	0	0
T45	0	25	0	0
T46	0	8	0	0
T143	0	15	0	0
T144	0	15	0	0
T145	0	5	0	0
T147	0	20	0	0
T148	0	20	0	0
T149	0	15	0	0
T150	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37286	0	0
T1	2287678	0	0	0
T2	0	266	0	0
T3	0	575	0	0
T4	1366712	0	0	0
T5	1300978	40	0	0
T6	19868	33	0	0
T7	37646	0	0	0
T17	70364	0	0	0
T18	58096	3	0	0
T19	37916	4	0	0
T20	77766	30	0	0
T21	32864	0	0	0
T24	0	9	0	0
T25	27102	0	0	0
T38	0	9	0	0
T45	0	42	0	0
T46	0	20	0	0
T109	0	9	0	0
T112	0	3	0	0
T143	0	27	0	0
T144	0	21	0	0
T145	0	7	0	0
T146	0	1	0	0
T147	0	24	0	0
T148	0	26	0	0
T149	0	19	0	0
T150	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206936213	142	0	0
CgEnOn_A	206936213	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936213	142	0	0
T1	101617	0	0	0
T4	42975	0	0	0
T6	876	3	0	0
T7	1771	0	0	0
T17	3095	0	0	0
T18	2538	0	0	0
T19	1669	0	0	0
T20	3447	3	0	0
T21	3442	0	0	0
T25	1222	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936213	142	0	0
T1	101617	0	0	0
T4	42975	0	0	0
T6	876	3	0	0
T7	1771	0	0	0
T17	3095	0	0	0
T18	2538	0	0	0
T19	1669	0	0	0
T20	3447	3	0	0
T21	3442	0	0	0
T25	1222	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103467486	142	0	0
CgEnOn_A	103467486	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103467486	142	0	0
CgEnOn_A	103467486	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103467486	142	0	0
CgEnOn_A	103467486	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	142	0	0
T1	50809	0	0	0
T4	21486	0	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T21	1721	0	0	0
T25	610	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	415561848	142	0	0
CgEnOn_A	415561848	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415561848	142	0	0
T1	203368	0	0	0
T4	129165	0	0	0
T6	1886	3	0	0
T7	3304	0	0	0
T17	6269	0	0	0
T18	5183	0	0	0
T19	3377	0	0	0
T20	6946	3	0	0
T21	6770	0	0	0
T25	2402	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415561848	134	0	0
T1	203368	0	0	0
T4	129165	0	0	0
T6	1886	3	0	0
T7	3304	0	0	0
T17	6269	0	0	0
T18	5183	0	0	0
T19	3377	0	0	0
T20	6946	3	0	0
T21	6770	0	0	0
T25	2402	0	0	0
T45	0	5	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	135	0	0
CgEnOn_A	443046840	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	135	0	0
T1	211849	0	0	0
T4	134553	0	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	0	0	0
T20	7212	2	0	0
T21	7052	0	0	0
T25	2502	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	130	0	0
T1	211849	0	0	0
T4	134553	0	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	0	0	0
T20	7212	2	0	0
T21	7052	0	0	0
T25	2502	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	135	0	0
CgEnOn_A	443046840	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	135	0	0
T1	211849	0	0	0
T4	134553	0	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	0	0	0
T20	7212	2	0	0
T21	7052	0	0	0
T25	2502	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	130	0	0
T1	211849	0	0	0
T4	134553	0	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	0	0	0
T20	7212	2	0	0
T21	7052	0	0	0
T25	2502	0	0	0
T45	0	2	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	6	0	0
T149	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	212569675	136	0	0
CgEnOn_A	212569675	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212569675	136	0	0
T1	101689	0	0	0
T4	64585	0	0	0
T6	944	4	0	0
T7	1652	0	0	0
T17	3134	0	0	0
T18	2592	0	0	0
T19	1688	0	0	0
T20	3408	3	0	0
T21	3385	0	0	0
T25	1201	0	0	0
T45	0	3	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212569675	135	0	0
T1	101689	0	0	0
T4	64585	0	0	0
T6	944	4	0	0
T7	1652	0	0	0
T17	3134	0	0	0
T18	2592	0	0	0
T19	1688	0	0	0
T20	3408	3	0	0
T21	3385	0	0	0
T25	1201	0	0	0
T45	0	3	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T45
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103467486	7437	0	0
CgEnOn_A	103467486	5093	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	7437	0	0
T1	50809	1	0	0
T4	21486	17	0	0
T5	39202	16	0	0
T6	438	4	0	0
T7	885	1	0	0
T17	1547	1	0	0
T18	1269	1	0	0
T19	835	1	0	0
T20	1723	4	0	0
T25	610	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467486	5093	0	0
T1	50809	0	0	0
T2	0	45	0	0
T3	0	131	0	0
T4	21486	0	0	0
T5	39202	13	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1547	0	0	0
T18	1269	0	0	0
T19	835	0	0	0
T20	1723	3	0	0
T25	610	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0
T144	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T45
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206936213	7426	0	0
CgEnOn_A	206936213	5082	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936213	7426	0	0
T1	101617	1	0	0
T4	42975	17	0	0
T5	78406	15	0	0
T6	876	4	0	0
T7	1771	1	0	0
T17	3095	1	0	0
T18	2538	1	0	0
T19	1669	2	0	0
T20	3447	4	0	0
T25	1222	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936213	5082	0	0
T1	101617	0	0	0
T2	0	46	0	0
T3	0	141	0	0
T4	42975	0	0	0
T5	78406	12	0	0
T6	876	3	0	0
T7	1771	0	0	0
T17	3095	0	0	0
T18	2538	0	0	0
T19	1669	1	0	0
T20	3447	3	0	0
T25	1222	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T45
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	415561848	7480	0	0
CgEnOn_A	415561848	5128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415561848	7480	0	0
T1	203368	1	0	0
T4	129165	17	0	0
T5	156647	16	0	0
T6	1886	4	0	0
T7	3304	1	0	0
T17	6269	1	0	0
T18	5183	1	0	0
T19	3377	2	0	0
T20	6946	4	0	0
T25	2402	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415561848	5128	0	0
T1	203368	0	0	0
T2	0	50	0	0
T3	0	131	0	0
T4	129165	0	0	0
T5	156647	13	0	0
T6	1886	3	0	0
T7	3304	0	0	0
T17	6269	0	0	0
T18	5183	0	0	0
T19	3377	1	0	0
T20	6946	3	0	0
T25	2402	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T45
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	212569675	7496	0	0
CgEnOn_A	212569675	5142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212569675	7496	0	0
T1	101689	1	0	0
T4	64585	17	0	0
T5	110007	16	0	0
T6	944	5	0	0
T7	1652	1	0	0
T17	3134	1	0	0
T18	2592	1	0	0
T19	1688	2	0	0
T20	3408	4	0	0
T25	1201	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212569675	5142	0	0
T1	101689	0	0	0
T2	0	50	0	0
T3	0	136	0	0
T4	64585	0	0	0
T5	110007	13	0	0
T6	944	4	0	0
T7	1652	0	0	0
T17	3134	0	0	0
T18	2592	0	0	0
T19	1688	1	0	0
T20	3408	3	0	0
T25	1201	0	0	0
T45	0	3	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	3951	0	0
CgEnOn_A	443046840	3946	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3951	0	0
T1	211849	0	0	0
T2	0	66	0	0
T3	0	88	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	3	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	7	0	0
T25	2502	0	0	0
T38	0	4	0	0
T46	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3946	0	0
T1	211849	0	0	0
T2	0	66	0	0
T3	0	88	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	3	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	7	0	0
T25	2502	0	0	0
T38	0	4	0	0
T46	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T19,T24
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	3946	0	0
CgEnOn_A	443046840	3941	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3946	0	0
T1	211849	0	0	0
T2	0	59	0	0
T3	0	84	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	6	0	0
T109	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3941	0	0
T1	211849	0	0	0
T2	0	59	0	0
T3	0	84	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	0	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	6	0	0
T109	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	3992	0	0
CgEnOn_A	443046840	3987	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3992	0	0
T1	211849	0	0	0
T2	0	65	0	0
T3	0	73	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	3	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3987	0	0
T1	211849	0	0	0
T2	0	65	0	0
T3	0	73	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	3	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443046840	3875	0	0
CgEnOn_A	443046840	3870	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3875	0	0
T1	211849	0	0	0
T2	0	68	0	0
T3	0	82	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	4	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	6	0	0
T25	2502	0	0	0
T38	0	3	0	0
T46	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443046840	3870	0	0
T1	211849	0	0	0
T2	0	68	0	0
T3	0	82	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	3	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5399	4	0	0
T19	3518	1	0	0
T20	7212	2	0	0
T24	0	6	0	0
T25	2502	0	0	0
T38	0	3	0	0
T46	0	8	0	0