Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	682325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3984604

1

T4

268

T1

529

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1139527	1			T4	288		T1	139		T5	8
values[0x0]	1619257	1			T4	142		T1	508		T5	8
values[0x1]	1908145	1			T4	134		T1	510		T5	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	371320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4295609

1

T4

335

T1

696

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19456	1			T4	1		T1	9		T19	1
valid_sources[0x01]	17975	1			T4	2		T1	6		T2	269
valid_sources[0x02]	17995	1			T4	6		T1	4		T2	261
valid_sources[0x03]	20458	1			T4	4		T1	2		T2	250
valid_sources[0x04]	18563	1			T1	2		T2	257		T3	211
valid_sources[0x05]	18907	1			T4	2		T1	5		T2	229
valid_sources[0x06]	18485	1			T4	4		T1	11		T2	240
valid_sources[0x07]	18771	1			T4	2		T1	4		T2	265
valid_sources[0x08]	18785	1			T4	5		T1	3		T5	2
valid_sources[0x09]	20882	1			T1	3		T2	246		T3	156
valid_sources[0x0a]	17485	1			T1	4		T17	1		T2	247
valid_sources[0x0b]	18674	1			T4	6		T1	4		T2	260
valid_sources[0x0c]	16478	1			T4	2		T1	2		T2	261
valid_sources[0x0d]	19439	1			T4	5		T1	4		T2	237
valid_sources[0x0e]	17585	1			T4	2		T1	1		T2	249
valid_sources[0x0f]	17278	1			T1	1		T2	239		T3	152
valid_sources[0x10]	17986	1			T4	4		T1	6		T2	231
valid_sources[0x11]	16265	1			T4	1		T1	3		T2	272
valid_sources[0x12]	17495	1			T1	2		T17	4		T2	230
valid_sources[0x13]	16887	1			T4	1		T1	3		T2	279
valid_sources[0x14]	17282	1			T4	3		T17	10		T2	281
valid_sources[0x15]	17883	1			T4	4		T1	4		T2	203
valid_sources[0x16]	19174	1			T4	1		T1	6		T2	253
valid_sources[0x17]	17309	1			T4	4		T1	4		T2	245
valid_sources[0x18]	19122	1			T4	3		T1	1		T19	1
valid_sources[0x19]	18474	1			T4	3		T1	6		T2	215
valid_sources[0x1a]	19258	1			T4	2		T1	1		T2	217
valid_sources[0x1b]	19210	1			T4	2		T1	2		T2	237
valid_sources[0x1c]	18150	1			T4	2		T1	4		T2	216
valid_sources[0x1d]	18628	1			T4	1		T1	3		T2	255
valid_sources[0x1e]	18068	1			T4	5		T1	4		T2	245
valid_sources[0x1f]	17380	1			T4	1		T1	6		T17	3
valid_sources[0x20]	17287	1			T4	6		T1	3		T2	281
valid_sources[0x21]	19011	1			T4	2		T1	1		T19	3
valid_sources[0x22]	17173	1			T4	3		T1	7		T17	1
valid_sources[0x23]	17297	1			T4	3		T1	7		T2	286
valid_sources[0x24]	18267	1			T4	3		T1	12		T17	5
valid_sources[0x25]	18173	1			T4	4		T1	6		T5	1
valid_sources[0x26]	17943	1			T4	1		T1	6		T2	260
valid_sources[0x27]	19769	1			T4	4		T1	8		T2	269
valid_sources[0x28]	18817	1			T4	1		T1	5		T2	250
valid_sources[0x29]	18268	1			T4	4		T1	1		T2	211
valid_sources[0x2a]	18921	1			T4	4		T1	2		T19	1
valid_sources[0x2b]	18240	1			T4	6		T1	2		T2	275
valid_sources[0x2c]	17175	1			T4	2		T1	8		T5	1
valid_sources[0x2d]	17908	1			T4	6		T1	11		T2	253
valid_sources[0x2e]	17845	1			T1	1		T2	250		T3	236
valid_sources[0x2f]	19718	1			T4	1		T1	8		T2	207
valid_sources[0x30]	18680	1			T4	2		T1	6		T2	264
valid_sources[0x31]	18810	1			T2	226		T3	221		T9	262
valid_sources[0x32]	17385	1			T4	8		T1	5		T2	248
valid_sources[0x33]	17603	1			T4	2		T1	7		T2	240
valid_sources[0x34]	16037	1			T4	2		T1	1		T2	234
valid_sources[0x35]	17304	1			T4	1		T1	4		T2	268
valid_sources[0x36]	19106	1			T4	3		T1	4		T2	281
valid_sources[0x37]	18332	1			T4	3		T1	3		T2	238
valid_sources[0x38]	17527	1			T4	1		T1	10		T5	1
valid_sources[0x39]	17815	1			T4	2		T1	6		T2	288
valid_sources[0x3a]	17368	1			T4	4		T1	5		T2	233
valid_sources[0x3b]	20054	1			T4	4		T1	8		T2	235
valid_sources[0x3c]	19186	1			T1	3		T19	1		T2	262
valid_sources[0x3d]	17749	1			T1	1		T2	272		T3	287
valid_sources[0x3e]	17340	1			T4	1		T1	2		T17	5
valid_sources[0x3f]	18374	1			T4	1		T1	2		T17	4
valid_sources[0x40]	18821	1			T4	3		T1	6		T2	290
valid_sources[0x41]	17501	1			T4	4		T2	231		T3	248
valid_sources[0x42]	19141	1			T4	7		T1	4		T5	2
valid_sources[0x43]	19034	1			T1	9		T2	261		T3	213
valid_sources[0x44]	18867	1			T4	1		T1	4		T2	250
valid_sources[0x45]	18943	1			T4	1		T1	10		T17	2
valid_sources[0x46]	20019	1			T4	3		T1	4		T2	271
valid_sources[0x47]	16904	1			T4	3		T1	3		T5	1
valid_sources[0x48]	18277	1			T4	2		T1	1		T2	246
valid_sources[0x49]	17532	1			T4	2		T1	2		T2	268
valid_sources[0x4a]	18191	1			T4	1		T1	5		T2	239
valid_sources[0x4b]	18378	1			T4	2		T1	5		T2	233
valid_sources[0x4c]	16604	1			T4	1		T1	3		T2	250
valid_sources[0x4d]	20024	1			T4	2		T1	19		T2	229
valid_sources[0x4e]	17477	1			T4	1		T1	8		T2	252
valid_sources[0x4f]	18859	1			T4	1		T1	4		T19	1
valid_sources[0x50]	18919	1			T1	7		T2	267		T3	224
valid_sources[0x51]	17960	1			T1	4		T2	228		T3	259
valid_sources[0x52]	18403	1			T4	2		T1	3		T2	262
valid_sources[0x53]	17486	1			T4	2		T1	2		T2	262
valid_sources[0x54]	17429	1			T4	5		T2	275		T3	196
valid_sources[0x55]	17148	1			T4	3		T1	12		T17	2
valid_sources[0x56]	16816	1			T4	2		T1	9		T2	226
valid_sources[0x57]	17036	1			T1	2		T19	1		T2	226
valid_sources[0x58]	18278	1			T4	2		T1	7		T17	1
valid_sources[0x59]	18130	1			T4	3		T1	1		T2	249
valid_sources[0x5a]	16105	1			T1	10		T17	1		T2	241
valid_sources[0x5b]	18393	1			T4	3		T1	1		T2	226
valid_sources[0x5c]	18741	1			T4	1		T1	1		T2	224
valid_sources[0x5d]	17111	1			T4	4		T1	4		T5	2
valid_sources[0x5e]	18788	1			T4	3		T1	1		T2	271
valid_sources[0x5f]	18201	1			T4	4		T1	5		T2	260
valid_sources[0x60]	18940	1			T2	224		T3	200		T9	193
valid_sources[0x61]	17298	1			T4	3		T2	233		T3	230
valid_sources[0x62]	16856	1			T4	1		T1	8		T5	1
valid_sources[0x63]	18301	1			T4	1		T1	8		T2	266
valid_sources[0x64]	16753	1			T4	2		T1	2		T2	217
valid_sources[0x65]	19669	1			T4	2		T1	4		T17	5
valid_sources[0x66]	18035	1			T4	2		T1	1		T2	266
valid_sources[0x67]	18241	1			T4	1		T1	5		T2	235
valid_sources[0x68]	18561	1			T4	4		T1	10		T2	249
valid_sources[0x69]	18874	1			T4	1		T1	7		T5	1
valid_sources[0x6a]	17441	1			T4	2		T1	2		T2	241
valid_sources[0x6b]	17447	1			T4	2		T1	4		T2	287
valid_sources[0x6c]	17104	1			T4	1		T1	5		T2	291
valid_sources[0x6d]	17428	1			T4	4		T1	2		T2	275
valid_sources[0x6e]	17556	1			T4	2		T1	4		T2	245
valid_sources[0x6f]	16569	1			T4	1		T1	1		T2	260
valid_sources[0x70]	18181	1			T4	2		T1	4		T2	248
valid_sources[0x71]	19194	1			T1	6		T17	2		T2	291
valid_sources[0x72]	18389	1			T4	4		T1	6		T2	267
valid_sources[0x73]	18914	1			T4	1		T1	11		T2	216
valid_sources[0x74]	19426	1			T4	2		T1	1		T2	249
valid_sources[0x75]	17469	1			T4	5		T1	3		T2	256
valid_sources[0x76]	18874	1			T4	3		T1	4		T2	227
valid_sources[0x77]	19349	1			T4	3		T1	4		T2	243
valid_sources[0x78]	19265	1			T4	3		T1	3		T2	233
valid_sources[0x79]	17253	1			T4	1		T1	4		T2	268
valid_sources[0x7a]	18839	1			T4	1		T1	2		T2	259
valid_sources[0x7b]	17796	1			T4	1		T1	3		T2	251
valid_sources[0x7c]	17998	1			T4	2		T1	4		T2	236
valid_sources[0x7d]	18561	1			T4	2		T1	4		T2	265
valid_sources[0x7e]	17477	1			T4	2		T1	6		T2	248
valid_sources[0x7f]	16896	1			T1	6		T2	211		T3	176
valid_sources[0x80]	18537	1			T4	4		T1	10		T2	218

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1003324

1

T4

139

T1

74

T5

5

values[0x0]

all_enables

biggest_size

1516273

1

T4

85

T1

285

T5

1

values[0x1]

all_enables

biggest_size

1465007

1

T4

44

T1

170

T18

1