Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T20,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1240529455	14925	0	0
GateOpen_A	1240529455	21578	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240529455	14925	0	0
T2	2454762	100	0	0
T3	1701757	211	0	0
T9	2471856	277	0	0
T10	0	333	0	0
T12	0	112	0	0
T13	0	5	0	0
T16	3207	20	0	0
T17	7895	0	0	0
T18	3893	0	0	0
T19	11542	0	0	0
T20	18441	8	0	0
T21	61085	0	0	0
T26	5390	0	0	0
T37	0	11	0	0
T99	0	2	0	0
T155	0	20	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240529455	21578	0	0
T1	1036653	12	0	0
T2	2454762	116	0	0
T3	1701757	219	0	0
T4	144017	48	0	0
T5	4208	4	0	0
T9	0	293	0	0
T16	3207	24	0	0
T17	7895	0	0	0
T18	3893	0	0	0
T19	11542	4	0	0
T20	18441	12	0	0
T21	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T20,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	137227212	3540	0	0
GateOpen_A	137227212	5202	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137227212	3540	0	0
T2	453877	26	0	0
T3	314345	53	0	0
T9	438156	63	0	0
T10	0	80	0	0
T12	0	28	0	0
T13	0	3	0	0
T16	348	5	0	0
T17	871	0	0	0
T18	447	0	0	0
T19	1276	0	0	0
T20	2035	2	0	0
T21	4140	0	0	0
T26	593	0	0	0
T37	0	3	0	0
T155	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137227212	5202	0	0
T1	113241	3	0	0
T2	453877	30	0	0
T3	314345	55	0	0
T4	9504	12	0	0
T5	453	1	0	0
T9	0	67	0	0
T16	348	6	0	0
T17	871	0	0	0
T18	447	0	0	0
T19	1276	1	0	0
T20	2035	3	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T20,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	274455327	3805	0	0
GateOpen_A	274455327	5467	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	3805	0	0
T2	907755	24	0	0
T3	628691	57	0	0
T9	876319	71	0	0
T10	0	85	0	0
T12	0	27	0	0
T13	0	2	0	0
T16	695	5	0	0
T17	1742	0	0	0
T18	895	0	0	0
T19	2552	0	0	0
T20	4069	2	0	0
T21	8282	0	0	0
T26	1185	0	0	0
T37	0	3	0	0
T155	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	5467	0	0
T1	226484	3	0	0
T2	907755	28	0	0
T3	628691	59	0	0
T4	19010	12	0	0
T5	908	1	0	0
T9	0	75	0	0
T16	695	6	0	0
T17	1742	0	0	0
T18	895	0	0	0
T19	2552	1	0	0
T20	4069	3	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T20,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	548669632	3803	0	0
GateOpen_A	548669632	5468	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	3803	0	0
T2	181509	26	0	0
T3	125680	51	0	0
T9	175609	71	0	0
T10	0	82	0	0
T12	0	29	0	0
T16	1470	5	0	0
T17	3521	0	0	0
T18	1701	0	0	0
T19	5143	0	0	0
T20	8190	2	0	0
T21	32441	0	0	0
T26	2408	0	0	0
T37	0	3	0	0
T99	0	1	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	5468	0	0
T1	453093	3	0	0
T2	181509	30	0	0
T3	125680	53	0	0
T4	77001	12	0	0
T5	1898	1	0	0
T9	0	75	0	0
T16	1470	6	0	0
T17	3521	0	0	0
T18	1701	0	0	0
T19	5143	1	0	0
T20	8190	3	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T20,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	280177284	3777	0	0
GateOpen_A	280177284	5441	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280177284	3777	0	0
T2	911621	24	0	0
T3	633041	50	0	0
T9	981772	72	0	0
T10	0	86	0	0
T12	0	28	0	0
T16	694	5	0	0
T17	1761	0	0	0
T18	850	0	0	0
T19	2571	0	0	0
T20	4147	2	0	0
T21	16222	0	0	0
T26	1204	0	0	0
T37	0	2	0	0
T99	0	1	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280177284	5441	0	0
T1	243835	3	0	0
T2	911621	28	0	0
T3	633041	52	0	0
T4	38502	12	0	0
T5	949	1	0	0
T9	0	76	0	0
T16	694	6	0	0
T17	1761	0	0	0
T18	850	0	0	0
T19	2571	1	0	0
T20	4147	3	0	0
T21	0	4	0	0