Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	892205295	82803	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892205295	82803	0	0
T1	2611045	190	0	0
T2	1238755	464	0	0
T3	1123530	201	0	0
T5	9880	0	0	0
T9	0	697	0	0
T10	0	570	0	0
T11	0	44	0	0
T12	0	143	0	0
T13	0	151	0	0
T14	0	62	0	0
T15	0	448	0	0
T16	7495	0	0	0
T17	17425	0	0	0
T18	8855	0	0	0
T19	5890	0	0	0
T20	4890	0	0	0
T21	167280	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178441059	12185	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	12185	0	0
T1	522209	28	0	0
T2	247751	83	0	0
T3	224706	33	0	0
T5	1976	0	0	0
T9	0	103	0	0
T10	0	91	0	0
T11	0	7	0	0
T12	0	28	0	0
T13	0	20	0	0
T14	0	9	0	0
T15	0	82	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178441059	12031	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	12031	0	0
T1	522209	22	0	0
T2	247751	83	0	0
T3	224706	33	0	0
T5	1976	0	0	0
T9	0	86	0	0
T10	0	90	0	0
T11	0	7	0	0
T12	0	28	0	0
T13	0	21	0	0
T14	0	9	0	0
T15	0	82	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178441059	16638	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	16638	0	0
T1	522209	38	0	0
T2	247751	93	0	0
T3	224706	41	0	0
T5	1976	0	0	0
T9	0	135	0	0
T10	0	115	0	0
T11	0	9	0	0
T12	0	28	0	0
T13	0	31	0	0
T14	0	13	0	0
T15	0	85	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178441059	16603	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	16603	0	0
T1	522209	40	0	0
T2	247751	89	0	0
T3	224706	41	0	0
T5	1976	0	0	0
T9	0	142	0	0
T10	0	116	0	0
T11	0	9	0	0
T12	0	28	0	0
T13	0	30	0	0
T14	0	12	0	0
T15	0	88	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178441059	25346	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	25346	0	0
T1	522209	62	0	0
T2	247751	116	0	0
T3	224706	53	0	0
T5	1976	0	0	0
T9	0	231	0	0
T10	0	158	0	0
T11	0	12	0	0
T12	0	31	0	0
T13	0	49	0	0
T14	0	19	0	0
T15	0	111	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0