Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	178441059	175875616	0	0
AllClkBypReqTrue_A	178441059	135465	0	0
IoClkBypReqFalse_A	178441059	175792253	0	2415
IoClkBypReqTrue_A	178441059	214098	0	0
LcClkBypAckFalse_A	178441059	175885178	0	0
LcClkBypAckTrue_A	178441059	125903	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	175875616	0	0
T1	522209	521392	0	0
T2	247751	247257	0	0
T3	224706	224605	0	0
T4	20052	2516	0	0
T5	1976	1778	0	0
T16	1499	1380	0	0
T17	3485	3405	0	0
T18	1771	1494	0	0
T19	1178	1162	0	0
T20	978	959	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	135465	0	0
T1	522209	104	0	0
T2	247751	1891	0	0
T3	224706	867	0	0
T5	1976	0	0	0
T9	0	943	0	0
T10	0	944	0	0
T12	0	1183	0	0
T13	0	510	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	107	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T42	0	41	0	0
T46	0	37	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	175792253	0	2415
T1	522209	521297	0	3
T2	247751	247146	0	3
T3	224706	224541	0	3
T4	20052	2490	0	3
T5	1976	1591	0	3
T16	1499	1378	0	3
T17	3485	3403	0	3
T18	1771	1427	0	3
T19	1178	1160	0	3
T20	978	957	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	214098	0	0
T1	522209	191	0	0
T2	247751	2989	0	0
T3	224706	1489	0	0
T5	1976	185	0	0
T9	0	1533	0	0
T10	0	1626	0	0
T12	0	1732	0	0
T13	0	868	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	172	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T42	0	348	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	175885178	0	0
T1	522209	521354	0	0
T2	247751	247288	0	0
T3	224706	224605	0	0
T4	20052	2516	0	0
T5	1976	1727	0	0
T16	1499	1380	0	0
T17	3485	3405	0	0
T18	1771	1504	0	0
T19	1178	1162	0	0
T20	978	959	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	125903	0	0
T1	522209	142	0	0
T2	247751	1579	0	0
T3	224706	868	0	0
T5	1976	51	0	0
T9	0	746	0	0
T10	0	836	0	0
T12	0	1041	0	0
T13	0	627	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	97	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T42	0	166	0	0