Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	17094	0	0
TransStop_A	2147483647	8435	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17094	0	0
T1	2055944	35	0	0
T2	760152	134	0	0
T3	527524	320	0	0
T5	7908	0	0	0
T9	0	189	0	0
T10	0	259	0	0
T16	5852	0	0	0
T17	14672	32	0	0
T18	7088	0	0	0
T19	21428	0	0	0
T20	34736	0	0	0
T21	135176	0	0	0
T26	0	38	0	0
T27	0	16	0	0
T28	0	4	0	0
T98	0	30	0	0
T99	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8435	0	0
T1	2055944	14	0	0
T2	760152	57	0	0
T3	527524	151	0	0
T5	7908	0	0	0
T9	0	90	0	0
T10	0	112	0	0
T16	5852	0	0	0
T17	14672	16	0	0
T18	7088	0	0	0
T19	21428	0	0	0
T20	34736	0	0	0
T21	135176	0	0	0
T26	0	13	0	0
T27	0	11	0	0
T28	0	2	0	0
T98	0	16	0	0
T99	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	583982103	4245	0	0
TransStop_A	583982103	2100	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	4245	0	0
T1	513986	9	0	0
T2	190038	35	0	0
T3	131881	82	0	0
T5	1977	0	0	0
T9	0	53	0	0
T10	0	68	0	0
T16	1463	0	0	0
T17	3668	8	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	11	0	0
T27	0	4	0	0
T28	0	2	0	0
T98	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	2100	0	0
T1	513986	5	0	0
T2	190038	14	0	0
T3	131881	41	0	0
T5	1977	0	0	0
T9	0	26	0	0
T10	0	28	0	0
T16	1463	0	0	0
T17	3668	5	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	4	0	0
T27	0	3	0	0
T28	0	1	0	0
T98	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	583982103	4268	0	0
TransStop_A	583982103	2082	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	4268	0	0
T1	513986	11	0	0
T2	190038	32	0	0
T3	131881	87	0	0
T5	1977	0	0	0
T9	0	44	0	0
T10	0	61	0	0
T16	1463	0	0	0
T17	3668	8	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	9	0	0
T27	0	3	0	0
T98	0	5	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	2082	0	0
T1	513986	5	0	0
T2	190038	13	0	0
T3	131881	37	0	0
T5	1977	0	0	0
T9	0	20	0	0
T10	0	26	0	0
T16	1463	0	0	0
T17	3668	4	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T98	0	4	0	0
T99	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	583982103	4283	0	0
TransStop_A	583982103	2120	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	4283	0	0
T1	513986	6	0	0
T2	190038	34	0	0
T3	131881	78	0	0
T5	1977	0	0	0
T9	0	47	0	0
T10	0	63	0	0
T16	1463	0	0	0
T17	3668	7	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	9	0	0
T27	0	5	0	0
T28	0	2	0	0
T98	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	2120	0	0
T1	513986	1	0	0
T2	190038	16	0	0
T3	131881	36	0	0
T5	1977	0	0	0
T9	0	21	0	0
T10	0	29	0	0
T16	1463	0	0	0
T17	3668	4	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	0	1	0	0
T98	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	583982103	4298	0	0
TransStop_A	583982103	2133	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	4298	0	0
T1	513986	9	0	0
T2	190038	33	0	0
T3	131881	73	0	0
T5	1977	0	0	0
T9	0	45	0	0
T10	0	67	0	0
T16	1463	0	0	0
T17	3668	9	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	9	0	0
T27	0	4	0	0
T98	0	6	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583982103	2133	0	0
T1	513986	3	0	0
T2	190038	14	0	0
T3	131881	37	0	0
T5	1977	0	0	0
T9	0	23	0	0
T10	0	29	0	0
T16	1463	0	0	0
T17	3668	3	0	0
T18	1772	0	0	0
T19	5357	0	0	0
T20	8684	0	0	0
T21	33794	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T98	0	3	0	0
T99	0	1	0	0