Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	178441059	16903515	0	61

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	16903515	0	61
T1	522209	23680	0	0
T2	247751	952504	0	0
T3	224706	14119	0	0
T5	1976	0	0	0
T9	0	82419	0	0
T10	0	41049	0	0
T11	0	3632	0	1
T12	0	6630	0	0
T13	0	17030	0	0
T14	0	6708	0	1
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T22	0	763	0	1
T23	0	0	0	1
T31	0	0	0	1
T62	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1
T103	0	0	0	1