Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	179384973	5905269	0	0
clk_enables_rd_A	179384973	41624	0	0
clk_hints_rd_A	179384973	36637	0	0
extclk_ctrl_rd_A	179384973	44246	0	0
extclk_ctrl_regwen_rd_A	179384973	36463	0	0
jitter_enable_rd_A	179384973	51669	0	0
jitter_regwen_rd_A	179384973	38758	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	5905269	0	0
T2	247751	87059	0	0
T3	224706	72391	0	0
T9	204408	69826	0	0
T10	225651	110157	0	0
T11	22743	0	0	0
T12	0	102465	0	0
T15	0	68889	0	0
T20	978	0	0	0
T21	33456	0	0	0
T25	0	60366	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T58	0	108678	0	0
T59	0	242314	0	0
T60	0	132506	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	41624	0	0
T3	224706	1707	0	0
T9	204408	0	0	0
T10	225651	0	0	0
T11	22743	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T37	958	0	0	0
T125	0	2	0	0
T126	0	4	0	0
T127	0	10	0	0
T128	0	2	0	0
T129	0	5	0	0
T130	0	5	0	0
T131	0	1390	0	0
T132	0	1	0	0
T133	0	1499	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	36637	0	0
T3	224706	1243	0	0
T9	204408	0	0	0
T10	225651	0	0	0
T11	22743	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T37	958	0	0	0
T44	0	4	0	0
T125	0	4	0	0
T126	0	3	0	0
T127	0	4	0	0
T128	0	4	0	0
T130	0	10	0	0
T131	0	1241	0	0
T132	0	2	0	0
T133	0	1488	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	44246	0	0
T2	247751	0	0	0
T3	224706	1542	0	0
T5	1976	24	0	0
T9	204408	0	0	0
T16	1499	0	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T76	0	22	0	0
T78	0	48	0	0
T134	0	5	0	0
T135	0	16	0	0
T136	0	29	0	0
T137	0	19	0	0
T138	0	24	0	0
T139	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	36463	0	0
T3	224706	1236	0	0
T9	204408	0	0	0
T10	225651	0	0	0
T11	22743	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T37	958	0	0	0
T131	0	1385	0	0
T133	0	1364	0	0
T138	0	8	0	0
T140	0	47	0	0
T141	0	44	0	0
T142	0	2149	0	0
T143	0	21	0	0
T144	0	5318	0	0
T145	0	3073	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	51669	0	0
T3	224706	1577	0	0
T9	204408	0	0	0
T10	225651	0	0	0
T11	22743	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T37	958	0	0	0
T44	0	42	0	0
T125	0	127	0	0
T126	0	109	0	0
T127	0	30	0	0
T128	0	131	0	0
T129	0	133	0	0
T130	0	285	0	0
T131	0	1699	0	0
T132	0	66	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179384973	38758	0	0
T3	224706	1403	0	0
T9	204408	0	0	0
T10	225651	0	0	0
T11	22743	0	0	0
T20	978	0	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T27	1514	0	0	0
T28	1017	0	0	0
T37	958	0	0	0
T131	0	1371	0	0
T133	0	1456	0	0
T142	0	2356	0	0
T144	0	5411	0	0
T145	0	3569	0	0
T146	0	3368	0	0
T147	0	2826	0	0
T148	0	3967	0	0
T149	0	619	0	0