Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T2,T3
1	1	Covered	T1,T5,T18

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	548669632	4628	0	0
g_div2.Div2Whole_A	548669632	5509	0	0
g_div4.Div4Stepped_A	274455327	4530	0	0
g_div4.Div4Whole_A	274455327	5178	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	4628	0	0
T1	453093	5	0	0
T2	181509	58	0	0
T3	125680	24	0	0
T5	1898	1	0	0
T9	0	25	0	0
T10	0	50	0	0
T12	0	55	0	0
T13	0	20	0	0
T16	1470	0	0	0
T17	3521	0	0	0
T18	1701	3	0	0
T19	5143	0	0	0
T20	8190	0	0	0
T21	32441	0	0	0
T42	0	7	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	5509	0	0
T1	453093	7	0	0
T2	181509	60	0	0
T3	125680	24	0	0
T5	1898	4	0	0
T9	0	43	0	0
T10	0	55	0	0
T12	0	55	0	0
T13	0	25	0	0
T16	1470	0	0	0
T17	3521	0	0	0
T18	1701	3	0	0
T19	5143	0	0	0
T20	8190	0	0	0
T21	32441	0	0	0
T42	0	9	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	4530	0	0
T1	226484	4	0	0
T2	907755	57	0	0
T3	628691	24	0	0
T5	908	1	0	0
T9	0	24	0	0
T10	0	50	0	0
T12	0	55	0	0
T13	0	20	0	0
T16	695	0	0	0
T17	1742	0	0	0
T18	895	3	0	0
T19	2552	0	0	0
T20	4069	0	0	0
T21	8282	0	0	0
T42	0	7	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	5178	0	0
T1	226484	3	0	0
T2	907755	60	0	0
T3	628691	24	0	0
T5	908	4	0	0
T9	0	38	0	0
T10	0	54	0	0
T12	0	55	0	0
T13	0	25	0	0
T16	695	0	0	0
T17	1742	0	0	0
T18	895	3	0	0
T19	2552	0	0	0
T20	4069	0	0	0
T21	8282	0	0	0
T42	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T2,T3
1	1	Covered	T1,T5,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	548669632	4628	0	0
g_div2.Div2Whole_A	548669632	5509	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	4628	0	0
T1	453093	5	0	0
T2	181509	58	0	0
T3	125680	24	0	0
T5	1898	1	0	0
T9	0	25	0	0
T10	0	50	0	0
T12	0	55	0	0
T13	0	20	0	0
T16	1470	0	0	0
T17	3521	0	0	0
T18	1701	3	0	0
T19	5143	0	0	0
T20	8190	0	0	0
T21	32441	0	0	0
T42	0	7	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669632	5509	0	0
T1	453093	7	0	0
T2	181509	60	0	0
T3	125680	24	0	0
T5	1898	4	0	0
T9	0	43	0	0
T10	0	55	0	0
T12	0	55	0	0
T13	0	25	0	0
T16	1470	0	0	0
T17	3521	0	0	0
T18	1701	3	0	0
T19	5143	0	0	0
T20	8190	0	0	0
T21	32441	0	0	0
T42	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T2,T3
1	1	Covered	T1,T5,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	274455327	4530	0	0
g_div4.Div4Whole_A	274455327	5178	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	4530	0	0
T1	226484	4	0	0
T2	907755	57	0	0
T3	628691	24	0	0
T5	908	1	0	0
T9	0	24	0	0
T10	0	50	0	0
T12	0	55	0	0
T13	0	20	0	0
T16	695	0	0	0
T17	1742	0	0	0
T18	895	3	0	0
T19	2552	0	0	0
T20	4069	0	0	0
T21	8282	0	0	0
T42	0	7	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274455327	5178	0	0
T1	226484	3	0	0
T2	907755	60	0	0
T3	628691	24	0	0
T5	908	4	0	0
T9	0	38	0	0
T10	0	54	0	0
T12	0	55	0	0
T13	0	25	0	0
T16	695	0	0	0
T17	1742	0	0	0
T18	895	3	0	0
T19	2552	0	0	0
T20	4069	0	0	0
T21	8282	0	0	0
T42	0	9	0	0