Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	535323177	447	0	0
StatusRise_A	535323177	447	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535323177	447	0	0
T2	743253	0	0	0
T3	674118	0	0	0
T9	613224	0	0	0
T16	4497	13	0	0
T17	10455	0	0	0
T18	5313	0	0	0
T19	3534	0	0	0
T20	2934	6	0	0
T21	100368	0	0	0
T26	7524	0	0	0
T37	0	9	0	0
T43	0	6	0	0
T77	0	16	0	0
T150	0	10	0	0
T151	0	4	0	0
T152	0	8	0	0
T153	0	3	0	0
T154	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535323177	447	0	0
T2	743253	0	0	0
T3	674118	0	0	0
T9	613224	0	0	0
T16	4497	13	0	0
T17	10455	0	0	0
T18	5313	0	0	0
T19	3534	0	0	0
T20	2934	6	0	0
T21	100368	0	0	0
T26	7524	0	0	0
T37	0	9	0	0
T43	0	6	0	0
T77	0	16	0	0
T150	0	10	0	0
T151	0	4	0	0
T152	0	8	0	0
T153	0	3	0	0
T154	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	178441059	155	0	0
StatusRise_A	178441059	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	155	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	3	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	155	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	3	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	178441059	146	0	0
StatusRise_A	178441059	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	146	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	5	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	146	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	5	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	178441059	146	0	0
StatusRise_A	178441059	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	146	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	5	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	2	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178441059	146	0	0
T2	247751	0	0	0
T3	224706	0	0	0
T9	204408	0	0	0
T16	1499	5	0	0
T17	3485	0	0	0
T18	1771	0	0	0
T19	1178	0	0	0
T20	978	2	0	0
T21	33456	0	0	0
T26	2508	0	0	0
T37	0	2	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0