Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51777	0	0
CgEnOn_A	2147483647	42304	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51777	0	0
T1	3092596	21	0	0
T2	6957504	162	0	0
T3	4823490	343	0	0
T4	144015	39	0	0
T5	12111	3	0	0
T9	3753631	53	0	0
T10	0	68	0	0
T15	0	5	0	0
T16	15882	46	0	0
T17	39538	11	0	0
T18	19300	3	0	0
T19	57770	3	0	0
T20	93050	21	0	0
T21	272121	0	0	0
T26	11588	11	0	0
T37	0	15	0	0
T43	0	10	0	0
T77	0	25	0	0
T150	0	20	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42304	0	0
T1	2055944	9	0	0
T2	6957504	144	0	0
T3	4823490	325	0	0
T5	7904	0	0	0
T9	6225486	347	0	0
T10	0	442	0	0
T12	0	153	0	0
T13	0	8	0	0
T15	0	4	0	0
T16	15882	43	0	0
T17	39538	8	0	0
T18	19300	0	0	0
T19	57770	0	0	0
T20	93050	18	0	0
T21	333204	0	0	0
T26	16976	0	0	0
T37	0	24	0	0
T43	0	10	0	0
T77	0	25	0	0
T99	0	1	0	0
T150	0	20	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	274454922	152	0	0
CgEnOn_A	274454922	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274454922	152	0	0
T2	907754	0	0	0
T3	628691	0	0	0
T9	876318	0	0	0
T15	0	1	0	0
T16	695	5	0	0
T17	1741	0	0	0
T18	894	0	0	0
T19	2552	0	0	0
T20	4069	2	0	0
T21	8282	0	0	0
T26	1185	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274454922	152	0	0
T2	907754	0	0	0
T3	628691	0	0	0
T9	876318	0	0	0
T15	0	1	0	0
T16	695	5	0	0
T17	1741	0	0	0
T18	894	0	0	0
T19	2552	0	0	0
T20	4069	2	0	0
T21	8282	0	0	0
T26	1185	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	137226800	152	0	0
CgEnOn_A	137226800	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	137226800	152	0	0
CgEnOn_A	137226800	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	137226800	152	0	0
CgEnOn_A	137226800	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	152	0	0
T2	453877	0	0	0
T3	314345	0	0	0
T9	438156	0	0	0
T15	0	1	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	548669195	152	0	0
CgEnOn_A	548669195	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669195	152	0	0
T2	181509	0	0	0
T3	125680	0	0	0
T9	175609	0	0	0
T15	0	1	0	0
T16	1469	5	0	0
T17	3521	0	0	0
T18	1701	0	0	0
T19	5142	0	0	0
T20	8189	2	0	0
T21	32440	0	0	0
T26	2408	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669195	146	0	0
T2	181509	0	0	0
T3	125680	0	0	0
T9	175609	0	0	0
T16	1469	5	0	0
T17	3521	0	0	0
T18	1701	0	0	0
T19	5142	0	0	0
T20	8189	2	0	0
T21	32440	0	0	0
T26	2408	0	0	0
T37	0	3	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	160	0	0
CgEnOn_A	583981666	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	160	0	0
T2	190038	0	0	0
T3	131881	0	0	0
T9	202732	0	0	0
T16	1463	3	0	0
T17	3668	0	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	157	0	0
T2	190038	0	0	0
T3	131881	0	0	0
T9	202732	0	0	0
T16	1463	3	0	0
T17	3668	0	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	160	0	0
CgEnOn_A	583981666	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	160	0	0
T2	190038	0	0	0
T3	131881	0	0	0
T9	202732	0	0	0
T16	1463	3	0	0
T17	3668	0	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	157	0	0
T2	190038	0	0	0
T3	131881	0	0	0
T9	202732	0	0	0
T16	1463	3	0	0
T17	3668	0	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	2508	0	0	0
T37	0	4	0	0
T43	0	2	0	0
T77	0	6	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	280176880	149	0	0
CgEnOn_A	280176880	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280176880	149	0	0
T2	911621	0	0	0
T3	633041	0	0	0
T9	981772	0	0	0
T16	694	5	0	0
T17	1761	0	0	0
T18	850	0	0	0
T19	2571	0	0	0
T20	4147	2	0	0
T21	16221	0	0	0
T26	1203	0	0	0
T37	0	2	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280176880	147	0	0
T2	911621	0	0	0
T3	633041	0	0	0
T9	981772	0	0	0
T16	694	5	0	0
T17	1761	0	0	0
T18	850	0	0	0
T19	2571	0	0	0
T20	4147	2	0	0
T21	16221	0	0	0
T26	1203	0	0	0
T37	0	2	0	0
T43	0	2	0	0
T77	0	5	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T20,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	137226800	8157	0	0
CgEnOn_A	137226800	5798	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	8157	0	0
T1	113241	4	0	0
T2	453877	42	0	0
T3	314345	85	0	0
T4	9503	13	0	0
T5	453	1	0	0
T16	347	6	0	0
T17	871	1	0	0
T18	446	1	0	0
T19	1276	1	0	0
T20	2034	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137226800	5798	0	0
T2	453877	36	0	0
T3	314345	79	0	0
T9	438156	99	0	0
T10	0	125	0	0
T12	0	50	0	0
T13	0	4	0	0
T16	347	5	0	0
T17	871	0	0	0
T18	446	0	0	0
T19	1276	0	0	0
T20	2034	2	0	0
T21	4140	0	0	0
T26	592	0	0	0
T37	0	3	0	0
T155	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T20,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	274454922	8188	0	0
CgEnOn_A	274454922	5829	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274454922	8188	0	0
T1	226484	4	0	0
T2	907754	42	0	0
T3	628691	86	0	0
T4	19010	13	0	0
T5	908	1	0	0
T16	695	6	0	0
T17	1741	1	0	0
T18	894	1	0	0
T19	2552	1	0	0
T20	4069	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274454922	5829	0	0
T2	907754	36	0	0
T3	628691	80	0	0
T9	876318	95	0	0
T10	0	126	0	0
T12	0	51	0	0
T13	0	4	0	0
T16	695	5	0	0
T17	1741	0	0	0
T18	894	0	0	0
T19	2552	0	0	0
T20	4069	2	0	0
T21	8282	0	0	0
T26	1185	0	0	0
T37	0	3	0	0
T155	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T20,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	548669195	8261	0	0
CgEnOn_A	548669195	5896	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669195	8261	0	0
T1	453092	4	0	0
T2	181509	43	0	0
T3	125680	90	0	0
T4	77000	13	0	0
T5	1898	1	0	0
T16	1469	6	0	0
T17	3521	1	0	0
T18	1701	1	0	0
T19	5142	1	0	0
T20	8189	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548669195	5896	0	0
T2	181509	37	0	0
T3	125680	84	0	0
T9	175609	100	0	0
T10	0	123	0	0
T12	0	52	0	0
T16	1469	5	0	0
T17	3521	0	0	0
T18	1701	0	0	0
T19	5142	0	0	0
T20	8189	2	0	0
T21	32440	0	0	0
T26	2408	0	0	0
T37	0	3	0	0
T99	0	1	0	0
T155	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T20,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	280176880	8208	0	0
CgEnOn_A	280176880	5844	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280176880	8208	0	0
T1	243835	4	0	0
T2	911621	43	0	0
T3	633041	87	0	0
T4	38502	13	0	0
T5	948	1	0	0
T16	694	6	0	0
T17	1761	1	0	0
T18	850	1	0	0
T19	2571	1	0	0
T20	4147	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280176880	5844	0	0
T2	911621	37	0	0
T3	633041	81	0	0
T9	981772	98	0	0
T10	0	122	0	0
T12	0	50	0	0
T16	694	5	0	0
T17	1761	0	0	0
T18	850	0	0	0
T19	2571	0	0	0
T20	4147	2	0	0
T21	16221	0	0	0
T26	1203	0	0	0
T37	0	2	0	0
T99	0	1	0	0
T155	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T17,T2
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	4405	0	0
CgEnOn_A	583981666	4402	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4405	0	0
T1	513986	9	0	0
T2	190038	35	0	0
T3	131881	82	0	0
T5	1976	0	0	0
T9	0	53	0	0
T10	0	68	0	0
T16	1463	3	0	0
T17	3668	8	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	11	0	0
T27	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4402	0	0
T1	513986	9	0	0
T2	190038	35	0	0
T3	131881	82	0	0
T5	1976	0	0	0
T9	0	53	0	0
T10	0	68	0	0
T16	1463	3	0	0
T17	3668	8	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	11	0	0
T27	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T17,T2
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	4428	0	0
CgEnOn_A	583981666	4425	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4428	0	0
T1	513986	11	0	0
T2	190038	32	0	0
T3	131881	87	0	0
T5	1976	0	0	0
T9	0	44	0	0
T10	0	61	0	0
T16	1463	3	0	0
T17	3668	8	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4425	0	0
T1	513986	11	0	0
T2	190038	32	0	0
T3	131881	87	0	0
T5	1976	0	0	0
T9	0	44	0	0
T10	0	61	0	0
T16	1463	3	0	0
T17	3668	8	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T17,T2
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	4443	0	0
CgEnOn_A	583981666	4440	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4443	0	0
T1	513986	6	0	0
T2	190038	34	0	0
T3	131881	78	0	0
T5	1976	0	0	0
T9	0	47	0	0
T10	0	63	0	0
T16	1463	3	0	0
T17	3668	7	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4440	0	0
T1	513986	6	0	0
T2	190038	34	0	0
T3	131881	78	0	0
T5	1976	0	0	0
T9	0	47	0	0
T10	0	63	0	0
T16	1463	3	0	0
T17	3668	7	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T17,T2
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	583981666	4458	0	0
CgEnOn_A	583981666	4455	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4458	0	0
T1	513986	9	0	0
T2	190038	33	0	0
T3	131881	73	0	0
T5	1976	0	0	0
T9	0	45	0	0
T10	0	67	0	0
T16	1463	3	0	0
T17	3668	9	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583981666	4455	0	0
T1	513986	9	0	0
T2	190038	33	0	0
T3	131881	73	0	0
T5	1976	0	0	0
T9	0	45	0	0
T10	0	67	0	0
T16	1463	3	0	0
T17	3668	9	0	0
T18	1771	0	0	0
T19	5356	0	0	0
T20	8684	2	0	0
T21	33793	0	0	0
T26	0	9	0	0
T27	0	4	0	0