Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	631756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3673070

1

T6

6

T7

3

T8

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1058211	1			T6	8		T8	7		T1	153
values[0x0]	1492403	1			T6	10		T7	5		T8	6
values[0x1]	1754212	1			T6	7		T7	6		T8	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3957059

1

T6

9

T7

6

T8

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17101	1			T1	1		T4	2		T2	1
valid_sources[0x01]	18793	1			T4	1		T3	97		T75	4
valid_sources[0x02]	16842	1			T1	2		T4	3		T3	122
valid_sources[0x03]	18067	1			T1	5		T2	1		T3	114
valid_sources[0x04]	15866	1			T1	2		T3	89		T12	9
valid_sources[0x05]	16519	1			T1	4		T2	1		T25	1
valid_sources[0x06]	16821	1			T1	3		T25	1		T3	103
valid_sources[0x07]	17979	1			T1	1		T3	107		T12	11
valid_sources[0x08]	15470	1			T1	1		T21	4		T2	1
valid_sources[0x09]	16670	1			T1	2		T4	1		T3	122
valid_sources[0x0a]	17120	1			T1	6		T4	3		T5	470
valid_sources[0x0b]	15780	1			T1	2		T4	2		T2	5
valid_sources[0x0c]	16807	1			T4	1		T20	5		T25	1
valid_sources[0x0d]	16536	1			T1	5		T4	1		T2	1
valid_sources[0x0e]	16325	1			T1	3		T19	1		T4	1
valid_sources[0x0f]	17125	1			T2	4		T3	113		T12	5
valid_sources[0x10]	16065	1			T1	3		T4	2		T33	2
valid_sources[0x11]	16523	1			T1	1		T4	1		T2	3
valid_sources[0x12]	16529	1			T1	5		T4	1		T2	1
valid_sources[0x13]	18109	1			T1	3		T4	2		T3	100
valid_sources[0x14]	19087	1			T1	1		T3	116		T12	12
valid_sources[0x15]	16693	1			T1	3		T3	103		T37	3
valid_sources[0x16]	17003	1			T1	6		T2	2		T3	116
valid_sources[0x17]	16771	1			T1	3		T25	2		T3	128
valid_sources[0x18]	15391	1			T8	2		T1	2		T4	1
valid_sources[0x19]	18789	1			T1	3		T4	2		T2	1
valid_sources[0x1a]	17169	1			T1	8		T4	1		T2	1
valid_sources[0x1b]	16528	1			T1	7		T4	1		T3	123
valid_sources[0x1c]	16583	1			T1	1		T2	2		T3	112
valid_sources[0x1d]	15041	1			T1	2		T25	1		T3	100
valid_sources[0x1e]	17777	1			T1	5		T4	1		T2	1
valid_sources[0x1f]	15967	1			T1	2		T4	1		T2	1
valid_sources[0x20]	16292	1			T1	1		T2	1		T25	1
valid_sources[0x21]	16830	1			T1	5		T4	5		T2	2
valid_sources[0x22]	15048	1			T1	1		T4	1		T2	3
valid_sources[0x23]	16383	1			T1	3		T2	4		T25	1
valid_sources[0x24]	17002	1			T1	2		T2	4		T3	119
valid_sources[0x25]	18510	1			T1	2		T4	1		T22	1
valid_sources[0x26]	15066	1			T1	3		T2	3		T33	4
valid_sources[0x27]	16907	1			T1	2		T4	1		T3	100
valid_sources[0x28]	16447	1			T1	5		T3	104		T12	8
valid_sources[0x29]	16396	1			T1	4		T4	2		T2	1
valid_sources[0x2a]	18752	1			T1	1		T4	7		T2	1
valid_sources[0x2b]	16858	1			T1	1		T3	117		T12	6
valid_sources[0x2c]	17145	1			T1	5		T4	5		T2	2
valid_sources[0x2d]	17423	1			T1	2		T2	7		T25	1
valid_sources[0x2e]	17318	1			T1	1		T4	1		T25	1
valid_sources[0x2f]	16648	1			T2	2		T3	106		T75	9
valid_sources[0x30]	17195	1			T19	1		T2	1		T3	110
valid_sources[0x31]	15540	1			T1	3		T25	2		T3	119
valid_sources[0x32]	17184	1			T1	2		T2	2		T3	99
valid_sources[0x33]	16880	1			T1	2		T3	111		T12	5
valid_sources[0x34]	16298	1			T1	1		T4	2		T2	2
valid_sources[0x35]	14800	1			T1	2		T2	1		T3	110
valid_sources[0x36]	17606	1			T1	5		T4	2		T2	6
valid_sources[0x37]	15385	1			T1	1		T4	2		T2	1
valid_sources[0x38]	16831	1			T1	1		T2	1		T3	104
valid_sources[0x39]	16824	1			T4	1		T3	102		T12	8
valid_sources[0x3a]	17326	1			T1	2		T20	2		T3	96
valid_sources[0x3b]	16784	1			T1	4		T25	1		T3	93
valid_sources[0x3c]	16842	1			T3	98		T37	2		T12	8
valid_sources[0x3d]	16585	1			T1	1		T2	2		T25	1
valid_sources[0x3e]	18701	1			T3	110		T76	2		T77	1
valid_sources[0x3f]	16444	1			T1	3		T19	1		T2	1
valid_sources[0x40]	18540	1			T1	2		T2	2		T25	1
valid_sources[0x41]	16310	1			T1	8		T4	4		T3	85
valid_sources[0x42]	17470	1			T1	2		T4	2		T2	1
valid_sources[0x43]	17821	1			T1	3		T3	97		T12	14
valid_sources[0x44]	16016	1			T1	5		T4	1		T25	1
valid_sources[0x45]	16848	1			T1	3		T4	5		T3	124
valid_sources[0x46]	17201	1			T1	1		T3	113		T12	12
valid_sources[0x47]	17728	1			T1	2		T22	1		T25	1
valid_sources[0x48]	16349	1			T1	5		T4	4		T2	1
valid_sources[0x49]	16820	1			T1	1		T4	1		T2	4
valid_sources[0x4a]	17496	1			T1	5		T20	6		T3	109
valid_sources[0x4b]	17331	1			T1	3		T2	2		T3	99
valid_sources[0x4c]	17108	1			T1	5		T2	1		T3	110
valid_sources[0x4d]	15578	1			T1	5		T4	1		T3	98
valid_sources[0x4e]	15947	1			T1	2		T20	2		T2	1
valid_sources[0x4f]	15264	1			T1	1		T4	1		T2	1
valid_sources[0x50]	16868	1			T1	3		T2	1		T3	110
valid_sources[0x51]	15969	1			T1	6		T4	1		T2	1
valid_sources[0x52]	16567	1			T1	2		T4	5		T2	4
valid_sources[0x53]	16274	1			T1	3		T2	2		T3	88
valid_sources[0x54]	16254	1			T1	2		T2	2		T25	2
valid_sources[0x55]	16750	1			T1	1		T3	109		T37	1
valid_sources[0x56]	16734	1			T1	3		T2	1		T25	1
valid_sources[0x57]	16537	1			T1	1		T3	90		T76	1
valid_sources[0x58]	17692	1			T1	2		T2	3		T25	1
valid_sources[0x59]	16265	1			T1	4		T2	1		T3	104
valid_sources[0x5a]	17123	1			T2	2		T3	105		T12	4
valid_sources[0x5b]	17712	1			T1	6		T4	2		T3	102
valid_sources[0x5c]	18241	1			T1	3		T25	1		T3	115
valid_sources[0x5d]	16536	1			T1	4		T4	5		T22	1
valid_sources[0x5e]	17478	1			T1	6		T4	1		T2	2
valid_sources[0x5f]	17475	1			T1	4		T4	1		T22	1
valid_sources[0x60]	17016	1			T1	1		T2	2		T25	1
valid_sources[0x61]	16349	1			T1	5		T4	2		T3	116
valid_sources[0x62]	16106	1			T1	3		T20	5		T3	103
valid_sources[0x63]	18187	1			T1	5		T4	2		T2	1
valid_sources[0x64]	17114	1			T1	1		T4	1		T3	121
valid_sources[0x65]	15763	1			T1	3		T3	105		T12	8
valid_sources[0x66]	16928	1			T1	2		T2	1		T3	104
valid_sources[0x67]	16074	1			T1	4		T4	1		T25	1
valid_sources[0x68]	16376	1			T1	7		T19	1		T23	1
valid_sources[0x69]	17140	1			T1	2		T4	5		T25	1
valid_sources[0x6a]	16391	1			T23	3		T3	102		T76	1
valid_sources[0x6b]	16377	1			T1	2		T2	1		T3	96
valid_sources[0x6c]	16867	1			T1	3		T4	7		T3	100
valid_sources[0x6d]	16576	1			T1	3		T4	3		T2	1
valid_sources[0x6e]	18078	1			T1	1		T3	114		T12	4
valid_sources[0x6f]	18953	1			T1	3		T3	91		T12	12
valid_sources[0x70]	18622	1			T2	1		T22	1		T3	123
valid_sources[0x71]	15937	1			T1	5		T4	1		T20	5
valid_sources[0x72]	17562	1			T1	5		T22	2		T25	1
valid_sources[0x73]	13830	1			T2	1		T3	121		T76	1
valid_sources[0x74]	17014	1			T1	2		T4	4		T2	2
valid_sources[0x75]	16705	1			T1	2		T4	2		T3	99
valid_sources[0x76]	16885	1			T1	2		T4	2		T2	1
valid_sources[0x77]	16903	1			T4	4		T20	2		T21	2
valid_sources[0x78]	16706	1			T8	1		T1	2		T2	1
valid_sources[0x79]	17291	1			T1	2		T25	1		T3	102
valid_sources[0x7a]	16932	1			T1	3		T4	1		T3	105
valid_sources[0x7b]	16655	1			T1	2		T4	1		T25	1
valid_sources[0x7c]	17177	1			T1	4		T4	1		T2	1
valid_sources[0x7d]	16979	1			T1	5		T4	1		T2	1
valid_sources[0x7e]	17600	1			T1	2		T3	119		T12	9
valid_sources[0x7f]	17866	1			T2	1		T3	90		T76	3
valid_sources[0x80]	15779	1			T1	1		T4	1		T2	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

927355

1

T6

3

T8

3

T1

84

values[0x0]

all_enables

biggest_size

1397035

1

T6

2

T7

3

T8

2

values[0x1]

all_enables

biggest_size

1348680

1

T6

1

T8

2

T1

89