Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1082255972	15391	0	0
GateOpen_A	1082255972	21554	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082255972	15391	0	0
T1	521030	4	0	0
T2	301569	0	0	0
T3	0	101	0	0
T4	63451	0	0	0
T5	132418	0	0	0
T12	0	64	0	0
T14	0	381	0	0
T19	4568	0	0	0
T20	18758	0	0	0
T21	7696	0	0	0
T22	12388	0	0	0
T23	3299	0	0	0
T24	3058	0	0	0
T34	0	12	0	0
T35	0	16	0	0
T37	0	4	0	0
T158	0	15	0	0
T159	0	37	0	0
T160	0	31	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082255972	21554	0	0
T1	521030	8	0	0
T2	301569	4	0	0
T4	63451	24	0	0
T5	132418	44	0	0
T6	4142	4	0	0
T7	9478	0	0	0
T8	20286	4	0	0
T19	4568	4	0	0
T20	18758	0	0	0
T21	7696	4	0	0
T23	0	4	0	0
T24	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	119555371	3679	0	0
GateOpen_A	119555371	5218	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119555371	3679	0	0
T1	57856	1	0	0
T2	33494	0	0	0
T3	0	24	0	0
T4	5196	0	0	0
T5	9332	0	0	0
T12	0	15	0	0
T14	0	78	0	0
T19	513	0	0	0
T20	2080	0	0	0
T21	849	0	0	0
T22	1404	0	0	0
T23	354	0	0	0
T24	334	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	4	0	0
T159	0	8	0	0
T160	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119555371	5218	0	0
T1	57856	2	0	0
T2	33494	1	0	0
T4	5196	6	0	0
T5	9332	11	0	0
T6	465	1	0	0
T7	1047	0	0	0
T8	2380	1	0	0
T19	513	1	0	0
T20	2080	0	0	0
T21	849	1	0	0
T23	0	1	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	239111664	3899	0	0
GateOpen_A	239111664	5438	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111664	3899	0	0
T1	115711	1	0	0
T2	66988	0	0	0
T3	0	24	0	0
T4	10389	0	0	0
T5	18663	0	0	0
T12	0	17	0	0
T14	0	99	0	0
T19	1025	0	0	0
T20	4160	0	0	0
T21	1698	0	0	0
T22	2810	0	0	0
T23	709	0	0	0
T24	667	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	4	0	0
T159	0	10	0	0
T160	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111664	5438	0	0
T1	115711	2	0	0
T2	66988	1	0	0
T4	10389	6	0	0
T5	18663	11	0	0
T6	932	1	0	0
T7	2093	0	0	0
T8	4761	1	0	0
T19	1025	1	0	0
T20	4160	0	0	0
T21	1698	1	0	0
T23	0	1	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	478978243	3904	0	0
GateOpen_A	478978243	5446	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478978243	3904	0	0
T1	231638	1	0	0
T2	134056	0	0	0
T3	0	26	0	0
T4	31910	0	0	0
T5	69614	0	0	0
T12	0	15	0	0
T14	0	105	0	0
T19	2020	0	0	0
T20	8345	0	0	0
T21	3433	0	0	0
T22	5449	0	0	0
T23	1491	0	0	0
T24	1371	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	3	0	0
T159	0	10	0	0
T160	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478978243	5446	0	0
T1	231638	2	0	0
T2	134056	1	0	0
T4	31910	6	0	0
T5	69614	11	0	0
T6	1830	1	0	0
T7	4225	0	0	0
T8	8763	1	0	0
T19	2020	1	0	0
T20	8345	0	0	0
T21	3433	1	0	0
T23	0	1	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	244610694	3909	0	0
GateOpen_A	244610694	5452	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610694	3909	0	0
T1	115825	1	0	0
T2	67031	0	0	0
T3	0	27	0	0
T4	15956	0	0	0
T5	34809	0	0	0
T12	0	17	0	0
T14	0	99	0	0
T19	1010	0	0	0
T20	4173	0	0	0
T21	1716	0	0	0
T22	2725	0	0	0
T23	745	0	0	0
T24	686	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	4	0	0
T159	0	9	0	0
T160	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610694	5452	0	0
T1	115825	2	0	0
T2	67031	1	0	0
T4	15956	6	0	0
T5	34809	11	0	0
T6	915	1	0	0
T7	2113	0	0	0
T8	4382	1	0	0
T19	1010	1	0	0
T20	4173	0	0	0
T21	1716	1	0	0
T23	0	1	0	0
T24	0	1	0	0