Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	780649545	71795	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780649545	71795	0	0
T1	1158185	597	0	0
T2	670275	188	0	0
T3	0	1238	0	0
T4	161220	0	0	0
T5	177665	0	0	0
T12	0	444	0	0
T13	0	152	0	0
T14	0	1892	0	0
T15	0	62	0	0
T16	0	88	0	0
T17	0	70	0	0
T18	0	695	0	0
T19	5050	0	0	0
T20	10425	0	0	0
T21	4465	0	0	0
T22	7375	0	0	0
T23	7760	0	0	0
T24	6785	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156129909	10578	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	10578	0	0
T1	231637	88	0	0
T2	134055	28	0	0
T3	0	175	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	76	0	0
T13	0	24	0	0
T14	0	243	0	0
T15	0	9	0	0
T16	0	14	0	0
T17	0	10	0	0
T18	0	94	0	0
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156129909	10430	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	10430	0	0
T1	231637	73	0	0
T2	134055	24	0	0
T3	0	174	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	76	0	0
T13	0	24	0	0
T14	0	273	0	0
T15	0	9	0	0
T16	0	14	0	0
T17	0	9	0	0
T18	0	94	0	0
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156129909	14446	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	14446	0	0
T1	231637	119	0	0
T2	134055	36	0	0
T3	0	278	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	89	0	0
T13	0	30	0	0
T14	0	372	0	0
T15	0	12	0	0
T16	0	18	0	0
T17	0	14	0	0
T18	0	141	0	0
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156129909	14411	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	14411	0	0
T1	231637	120	0	0
T2	134055	40	0	0
T3	0	242	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	90	0	0
T13	0	31	0	0
T14	0	377	0	0
T15	0	12	0	0
T16	0	17	0	0
T17	0	15	0	0
T18	0	138	0	0
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156129909	21930	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	21930	0	0
T1	231637	197	0	0
T2	134055	60	0	0
T3	0	369	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	113	0	0
T13	0	43	0	0
T14	0	627	0	0
T15	0	20	0	0
T16	0	25	0	0
T17	0	22	0	0
T18	0	228	0	0
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0