Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
6167255 |
6156846 |
0 |
0 |
T2 |
3569207 |
3564584 |
0 |
0 |
T4 |
845934 |
159210 |
0 |
0 |
T5 |
1352136 |
261921 |
0 |
0 |
T6 |
48728 |
45702 |
0 |
0 |
T7 |
67467 |
65665 |
0 |
0 |
T8 |
125256 |
122795 |
0 |
0 |
T19 |
39652 |
37956 |
0 |
0 |
T20 |
134527 |
133622 |
0 |
0 |
T21 |
55812 |
54510 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
936779454 |
922355934 |
0 |
14490 |
T1 |
1389822 |
1387236 |
0 |
18 |
T2 |
804330 |
803178 |
0 |
18 |
T4 |
193464 |
23346 |
0 |
18 |
T5 |
213198 |
25650 |
0 |
18 |
T6 |
10974 |
10230 |
0 |
18 |
T7 |
6072 |
5862 |
0 |
18 |
T8 |
6024 |
5868 |
0 |
18 |
T19 |
6060 |
5760 |
0 |
18 |
T20 |
12510 |
12396 |
0 |
18 |
T21 |
5358 |
5196 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1660099 |
1657006 |
0 |
21 |
T2 |
960749 |
959369 |
0 |
21 |
T4 |
229357 |
27671 |
0 |
21 |
T5 |
430744 |
51983 |
0 |
21 |
T6 |
13111 |
12223 |
0 |
21 |
T7 |
23848 |
23068 |
0 |
21 |
T8 |
47283 |
46164 |
0 |
21 |
T19 |
12451 |
11854 |
0 |
21 |
T20 |
47286 |
46891 |
0 |
21 |
T21 |
19522 |
18972 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
201775 |
0 |
0 |
T1 |
1660099 |
130 |
0 |
0 |
T2 |
960749 |
4 |
0 |
0 |
T3 |
0 |
208 |
0 |
0 |
T4 |
229357 |
24 |
0 |
0 |
T5 |
430744 |
44 |
0 |
0 |
T6 |
13111 |
91 |
0 |
0 |
T7 |
23848 |
12 |
0 |
0 |
T8 |
47283 |
67 |
0 |
0 |
T12 |
0 |
154 |
0 |
0 |
T19 |
12451 |
50 |
0 |
0 |
T20 |
47286 |
72 |
0 |
0 |
T21 |
19522 |
12 |
0 |
0 |
T22 |
0 |
57 |
0 |
0 |
T23 |
0 |
24 |
0 |
0 |
T77 |
0 |
127 |
0 |
0 |
T79 |
0 |
71 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3117334 |
3112487 |
0 |
0 |
T2 |
1804128 |
1801998 |
0 |
0 |
T4 |
423113 |
107959 |
0 |
0 |
T5 |
708194 |
183859 |
0 |
0 |
T6 |
24643 |
23210 |
0 |
0 |
T7 |
37547 |
36696 |
0 |
0 |
T8 |
71949 |
70724 |
0 |
0 |
T19 |
21141 |
20303 |
0 |
0 |
T20 |
74731 |
74296 |
0 |
0 |
T21 |
30932 |
30303 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478977807 |
474884164 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
31909 |
3867 |
0 |
0 |
T5 |
69614 |
8438 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
4224 |
4089 |
0 |
0 |
T8 |
8763 |
8559 |
0 |
0 |
T19 |
2019 |
1925 |
0 |
0 |
T20 |
8344 |
8278 |
0 |
0 |
T21 |
3432 |
3339 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478977807 |
474877453 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
31909 |
3849 |
0 |
3 |
T5 |
69614 |
8405 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
4224 |
4086 |
0 |
3 |
T8 |
8763 |
8556 |
0 |
3 |
T19 |
2019 |
1922 |
0 |
3 |
T20 |
8344 |
8275 |
0 |
3 |
T21 |
3432 |
3336 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478977807 |
28666 |
0 |
0 |
T1 |
231637 |
4 |
0 |
0 |
T2 |
134055 |
0 |
0 |
0 |
T3 |
0 |
91 |
0 |
0 |
T4 |
31909 |
0 |
0 |
0 |
T5 |
69614 |
0 |
0 |
0 |
T6 |
1829 |
26 |
0 |
0 |
T7 |
4224 |
0 |
0 |
0 |
T8 |
8763 |
19 |
0 |
0 |
T12 |
0 |
67 |
0 |
0 |
T19 |
2019 |
13 |
0 |
0 |
T20 |
8344 |
0 |
0 |
0 |
T21 |
3432 |
0 |
0 |
0 |
T22 |
0 |
35 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T77 |
0 |
45 |
0 |
0 |
T79 |
0 |
26 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
17980 |
0 |
0 |
T1 |
231637 |
4 |
0 |
0 |
T2 |
134055 |
0 |
0 |
0 |
T3 |
0 |
48 |
0 |
0 |
T4 |
32244 |
0 |
0 |
0 |
T5 |
35533 |
0 |
0 |
0 |
T6 |
1829 |
19 |
0 |
0 |
T7 |
1012 |
0 |
0 |
0 |
T8 |
1004 |
4 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T19 |
1010 |
10 |
0 |
0 |
T20 |
2085 |
0 |
0 |
0 |
T21 |
893 |
0 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T23 |
0 |
11 |
0 |
0 |
T77 |
0 |
44 |
0 |
0 |
T79 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T8,T1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T8,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
20279 |
0 |
0 |
T1 |
231637 |
4 |
0 |
0 |
T2 |
134055 |
0 |
0 |
0 |
T3 |
0 |
69 |
0 |
0 |
T4 |
32244 |
0 |
0 |
0 |
T5 |
35533 |
0 |
0 |
0 |
T6 |
1829 |
14 |
0 |
0 |
T7 |
1012 |
0 |
0 |
0 |
T8 |
1004 |
17 |
0 |
0 |
T12 |
0 |
45 |
0 |
0 |
T19 |
1010 |
9 |
0 |
0 |
T20 |
2085 |
0 |
0 |
0 |
T21 |
893 |
0 |
0 |
0 |
T22 |
0 |
9 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T77 |
0 |
38 |
0 |
0 |
T79 |
0 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
507657813 |
0 |
0 |
T1 |
241297 |
241070 |
0 |
0 |
T2 |
139646 |
139562 |
0 |
0 |
T4 |
33240 |
21643 |
0 |
0 |
T5 |
72516 |
38876 |
0 |
0 |
T6 |
1906 |
1822 |
0 |
0 |
T7 |
4400 |
4360 |
0 |
0 |
T8 |
9128 |
9030 |
0 |
0 |
T19 |
2103 |
2034 |
0 |
0 |
T20 |
8693 |
8667 |
0 |
0 |
T21 |
3576 |
3536 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
507657813 |
0 |
0 |
T1 |
241297 |
241070 |
0 |
0 |
T2 |
139646 |
139562 |
0 |
0 |
T4 |
33240 |
21643 |
0 |
0 |
T5 |
72516 |
38876 |
0 |
0 |
T6 |
1906 |
1822 |
0 |
0 |
T7 |
4400 |
4360 |
0 |
0 |
T8 |
9128 |
9030 |
0 |
0 |
T19 |
2103 |
2034 |
0 |
0 |
T20 |
8693 |
8667 |
0 |
0 |
T21 |
3576 |
3536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478977807 |
476927544 |
0 |
0 |
T1 |
231637 |
231421 |
0 |
0 |
T2 |
134055 |
133975 |
0 |
0 |
T4 |
31909 |
20776 |
0 |
0 |
T5 |
69614 |
37320 |
0 |
0 |
T6 |
1829 |
1749 |
0 |
0 |
T7 |
4224 |
4185 |
0 |
0 |
T8 |
8763 |
8669 |
0 |
0 |
T19 |
2019 |
1953 |
0 |
0 |
T20 |
8344 |
8319 |
0 |
0 |
T21 |
3432 |
3394 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478977807 |
476927544 |
0 |
0 |
T1 |
231637 |
231421 |
0 |
0 |
T2 |
134055 |
133975 |
0 |
0 |
T4 |
31909 |
20776 |
0 |
0 |
T5 |
69614 |
37320 |
0 |
0 |
T6 |
1829 |
1749 |
0 |
0 |
T7 |
4224 |
4185 |
0 |
0 |
T8 |
8763 |
8669 |
0 |
0 |
T19 |
2019 |
1953 |
0 |
0 |
T20 |
8344 |
8319 |
0 |
0 |
T21 |
3432 |
3394 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239111273 |
239111273 |
0 |
0 |
T1 |
115711 |
115711 |
0 |
0 |
T2 |
66988 |
66988 |
0 |
0 |
T4 |
10389 |
10389 |
0 |
0 |
T5 |
18662 |
18662 |
0 |
0 |
T6 |
932 |
932 |
0 |
0 |
T7 |
2093 |
2093 |
0 |
0 |
T8 |
4761 |
4761 |
0 |
0 |
T19 |
1025 |
1025 |
0 |
0 |
T20 |
4160 |
4160 |
0 |
0 |
T21 |
1697 |
1697 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239111273 |
239111273 |
0 |
0 |
T1 |
115711 |
115711 |
0 |
0 |
T2 |
66988 |
66988 |
0 |
0 |
T4 |
10389 |
10389 |
0 |
0 |
T5 |
18662 |
18662 |
0 |
0 |
T6 |
932 |
932 |
0 |
0 |
T7 |
2093 |
2093 |
0 |
0 |
T8 |
4761 |
4761 |
0 |
0 |
T19 |
1025 |
1025 |
0 |
0 |
T20 |
4160 |
4160 |
0 |
0 |
T21 |
1697 |
1697 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
119554971 |
119554971 |
0 |
0 |
T1 |
57855 |
57855 |
0 |
0 |
T2 |
33494 |
33494 |
0 |
0 |
T4 |
5196 |
5196 |
0 |
0 |
T5 |
9332 |
9332 |
0 |
0 |
T6 |
464 |
464 |
0 |
0 |
T7 |
1046 |
1046 |
0 |
0 |
T8 |
2380 |
2380 |
0 |
0 |
T19 |
512 |
512 |
0 |
0 |
T20 |
2080 |
2080 |
0 |
0 |
T21 |
849 |
849 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
119554971 |
119554971 |
0 |
0 |
T1 |
57855 |
57855 |
0 |
0 |
T2 |
33494 |
33494 |
0 |
0 |
T4 |
5196 |
5196 |
0 |
0 |
T5 |
9332 |
9332 |
0 |
0 |
T6 |
464 |
464 |
0 |
0 |
T7 |
1046 |
1046 |
0 |
0 |
T8 |
2380 |
2380 |
0 |
0 |
T19 |
512 |
512 |
0 |
0 |
T20 |
2080 |
2080 |
0 |
0 |
T21 |
849 |
849 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
244610269 |
243573838 |
0 |
0 |
T1 |
115824 |
115716 |
0 |
0 |
T2 |
67031 |
66991 |
0 |
0 |
T4 |
15955 |
10389 |
0 |
0 |
T5 |
34808 |
18661 |
0 |
0 |
T6 |
914 |
875 |
0 |
0 |
T7 |
2112 |
2092 |
0 |
0 |
T8 |
4381 |
4334 |
0 |
0 |
T19 |
1010 |
977 |
0 |
0 |
T20 |
4172 |
4160 |
0 |
0 |
T21 |
1716 |
1697 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
244610269 |
243573838 |
0 |
0 |
T1 |
115824 |
115716 |
0 |
0 |
T2 |
67031 |
66991 |
0 |
0 |
T4 |
15955 |
10389 |
0 |
0 |
T5 |
34808 |
18661 |
0 |
0 |
T6 |
914 |
875 |
0 |
0 |
T7 |
2112 |
2092 |
0 |
0 |
T8 |
4381 |
4334 |
0 |
0 |
T19 |
1010 |
977 |
0 |
0 |
T20 |
4172 |
4160 |
0 |
0 |
T21 |
1716 |
1697 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153725989 |
0 |
2415 |
T1 |
231637 |
231206 |
0 |
3 |
T2 |
134055 |
133863 |
0 |
3 |
T4 |
32244 |
3891 |
0 |
3 |
T5 |
35533 |
4275 |
0 |
3 |
T6 |
1829 |
1705 |
0 |
3 |
T7 |
1012 |
977 |
0 |
3 |
T8 |
1004 |
978 |
0 |
3 |
T19 |
1010 |
960 |
0 |
3 |
T20 |
2085 |
2066 |
0 |
3 |
T21 |
893 |
866 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
156129909 |
153732881 |
0 |
0 |
T1 |
231637 |
231215 |
0 |
0 |
T2 |
134055 |
133866 |
0 |
0 |
T4 |
32244 |
3909 |
0 |
0 |
T5 |
35533 |
4308 |
0 |
0 |
T6 |
1829 |
1708 |
0 |
0 |
T7 |
1012 |
980 |
0 |
0 |
T8 |
1004 |
981 |
0 |
0 |
T19 |
1010 |
963 |
0 |
0 |
T20 |
2085 |
2069 |
0 |
0 |
T21 |
893 |
869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505498232 |
0 |
2415 |
T1 |
241297 |
240847 |
0 |
3 |
T2 |
139646 |
139445 |
0 |
3 |
T4 |
33240 |
4010 |
0 |
3 |
T5 |
72516 |
8757 |
0 |
3 |
T6 |
1906 |
1777 |
0 |
3 |
T7 |
4400 |
4257 |
0 |
3 |
T8 |
9128 |
8913 |
0 |
3 |
T19 |
2103 |
2003 |
0 |
3 |
T20 |
8693 |
8621 |
0 |
3 |
T21 |
3576 |
3476 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
33769 |
0 |
0 |
T1 |
241297 |
29 |
0 |
0 |
T2 |
139646 |
1 |
0 |
0 |
T4 |
33240 |
6 |
0 |
0 |
T5 |
72516 |
11 |
0 |
0 |
T6 |
1906 |
5 |
0 |
0 |
T7 |
4400 |
3 |
0 |
0 |
T8 |
9128 |
5 |
0 |
0 |
T19 |
2103 |
5 |
0 |
0 |
T20 |
8693 |
19 |
0 |
0 |
T21 |
3576 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505498232 |
0 |
2415 |
T1 |
241297 |
240847 |
0 |
3 |
T2 |
139646 |
139445 |
0 |
3 |
T4 |
33240 |
4010 |
0 |
3 |
T5 |
72516 |
8757 |
0 |
3 |
T6 |
1906 |
1777 |
0 |
3 |
T7 |
4400 |
4257 |
0 |
3 |
T8 |
9128 |
8913 |
0 |
3 |
T19 |
2103 |
2003 |
0 |
3 |
T20 |
8693 |
8621 |
0 |
3 |
T21 |
3576 |
3476 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
33428 |
0 |
0 |
T1 |
241297 |
29 |
0 |
0 |
T2 |
139646 |
1 |
0 |
0 |
T4 |
33240 |
6 |
0 |
0 |
T5 |
72516 |
11 |
0 |
0 |
T6 |
1906 |
1 |
0 |
0 |
T7 |
4400 |
3 |
0 |
0 |
T8 |
9128 |
8 |
0 |
0 |
T19 |
2103 |
3 |
0 |
0 |
T20 |
8693 |
19 |
0 |
0 |
T21 |
3576 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505498232 |
0 |
2415 |
T1 |
241297 |
240847 |
0 |
3 |
T2 |
139646 |
139445 |
0 |
3 |
T4 |
33240 |
4010 |
0 |
3 |
T5 |
72516 |
8757 |
0 |
3 |
T6 |
1906 |
1777 |
0 |
3 |
T7 |
4400 |
4257 |
0 |
3 |
T8 |
9128 |
8913 |
0 |
3 |
T19 |
2103 |
2003 |
0 |
3 |
T20 |
8693 |
8621 |
0 |
3 |
T21 |
3576 |
3476 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
33770 |
0 |
0 |
T1 |
241297 |
31 |
0 |
0 |
T2 |
139646 |
1 |
0 |
0 |
T4 |
33240 |
6 |
0 |
0 |
T5 |
72516 |
11 |
0 |
0 |
T6 |
1906 |
15 |
0 |
0 |
T7 |
4400 |
3 |
0 |
0 |
T8 |
9128 |
8 |
0 |
0 |
T19 |
2103 |
3 |
0 |
0 |
T20 |
8693 |
15 |
0 |
0 |
T21 |
3576 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505498232 |
0 |
2415 |
T1 |
241297 |
240847 |
0 |
3 |
T2 |
139646 |
139445 |
0 |
3 |
T4 |
33240 |
4010 |
0 |
3 |
T5 |
72516 |
8757 |
0 |
3 |
T6 |
1906 |
1777 |
0 |
3 |
T7 |
4400 |
4257 |
0 |
3 |
T8 |
9128 |
8913 |
0 |
3 |
T19 |
2103 |
2003 |
0 |
3 |
T20 |
8693 |
8621 |
0 |
3 |
T21 |
3576 |
3476 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
33883 |
0 |
0 |
T1 |
241297 |
29 |
0 |
0 |
T2 |
139646 |
1 |
0 |
0 |
T4 |
33240 |
6 |
0 |
0 |
T5 |
72516 |
11 |
0 |
0 |
T6 |
1906 |
11 |
0 |
0 |
T7 |
4400 |
3 |
0 |
0 |
T8 |
9128 |
6 |
0 |
0 |
T19 |
2103 |
7 |
0 |
0 |
T20 |
8693 |
19 |
0 |
0 |
T21 |
3576 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
509820917 |
505505011 |
0 |
0 |
T1 |
241297 |
240856 |
0 |
0 |
T2 |
139646 |
139448 |
0 |
0 |
T4 |
33240 |
4028 |
0 |
0 |
T5 |
72516 |
8790 |
0 |
0 |
T6 |
1906 |
1780 |
0 |
0 |
T7 |
4400 |
4260 |
0 |
0 |
T8 |
9128 |
8916 |
0 |
0 |
T19 |
2103 |
2006 |
0 |
0 |
T20 |
8693 |
8624 |
0 |
0 |
T21 |
3576 |
3479 |
0 |
0 |