Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T4,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	156129909	153599698	0	0
AllClkBypReqTrue_A	156129909	130946	0	0
IoClkBypReqFalse_A	156129909	153517192	0	2415
IoClkBypReqTrue_A	156129909	208978	0	0
LcClkBypAckFalse_A	156129909	153607804	0	0
LcClkBypAckTrue_A	156129909	122840	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	153599698	0	0
T1	231637	231175	0	0
T2	134055	133865	0	0
T4	32244	3903	0	0
T5	35533	4297	0	0
T6	1829	1670	0	0
T7	1012	979	0	0
T8	1004	872	0	0
T19	1010	900	0	0
T20	2085	2068	0	0
T21	893	868	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	130946	0	0
T1	231637	37	0	0
T2	134055	0	0	0
T3	0	519	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T6	1829	37	0	0
T7	1012	0	0	0
T8	1004	108	0	0
T12	0	241	0	0
T19	1010	62	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	0	18	0	0
T23	0	76	0	0
T77	0	218	0	0
T79	0	270	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	153517192	0	2415
T1	231637	231165	0	3
T2	134055	133863	0	3
T4	32244	3891	0	3
T5	35533	4275	0	3
T6	1829	1561	0	3
T7	1012	977	0	3
T8	1004	931	0	3
T19	1010	875	0	3
T20	2085	2066	0	3
T21	893	866	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	208978	0	0
T1	231637	41	0	0
T2	134055	0	0	0
T3	0	683	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T6	1829	144	0	0
T7	1012	0	0	0
T8	1004	47	0	0
T12	0	529	0	0
T19	1010	85	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	0	189	0	0
T23	0	70	0	0
T77	0	373	0	0
T79	0	345	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	153607804	0	0
T1	231637	231212	0	0
T2	134055	133865	0	0
T4	32244	3903	0	0
T5	35533	4297	0	0
T6	1829	1640	0	0
T7	1012	979	0	0
T8	1004	937	0	0
T19	1010	918	0	0
T20	2085	2068	0	0
T21	893	868	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	122840	0	0
T1	231637	0	0	0
T2	134055	0	0	0
T3	0	390	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T6	1829	67	0	0
T7	1012	0	0	0
T8	1004	43	0	0
T12	0	320	0	0
T19	1010	44	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	0	75	0	0
T23	0	27	0	0
T77	0	144	0	0
T79	0	218	0	0
T80	0	151	0	0