Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2039285416	15418	0	0
TransStop_A	2039285416	7943	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039285416	15418	0	0
T1	965192	27	0	0
T2	558588	0	0	0
T3	0	61	0	0
T4	132964	0	0	0
T5	290068	0	0	0
T12	0	46	0	0
T19	8416	0	0	0
T20	34772	20	0	0
T21	14304	0	0	0
T22	22700	0	0	0
T23	6212	0	0	0
T24	5716	0	0	0
T33	0	19	0	0
T37	0	4	0	0
T75	0	17	0	0
T76	0	32	0	0
T78	0	41	0	0
T90	0	29	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039285416	7943	0	0
T1	965192	20	0	0
T2	558588	0	0	0
T3	0	27	0	0
T4	132964	0	0	0
T5	290068	0	0	0
T12	0	24	0	0
T19	8416	0	0	0
T20	34772	15	0	0
T21	14304	0	0	0
T22	22700	0	0	0
T23	6212	0	0	0
T24	5716	0	0	0
T33	0	11	0	0
T37	0	4	0	0
T75	0	6	0	0
T76	0	20	0	0
T78	0	24	0	0
T90	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	509821354	3828	0	0
TransStop_A	509821354	1984	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	3828	0	0
T1	241298	6	0	0
T2	139647	0	0	0
T3	0	10	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	11	0	0
T19	2104	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	5	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	7	0	0
T78	0	8	0	0
T90	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	1984	0	0
T1	241298	4	0	0
T2	139647	0	0	0
T3	0	5	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	5	0	0
T19	2104	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T78	0	5	0	0
T90	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	509821354	3932	0	0
TransStop_A	509821354	2036	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	3932	0	0
T1	241298	6	0	0
T2	139647	0	0	0
T3	0	19	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	13	0	0
T19	2104	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	4	0	0
T37	0	1	0	0
T75	0	6	0	0
T76	0	6	0	0
T78	0	13	0	0
T90	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	2036	0	0
T1	241298	4	0	0
T2	139647	0	0	0
T3	0	8	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	8	0	0
T19	2104	0	0	0
T20	8693	3	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T75	0	3	0	0
T76	0	4	0	0
T78	0	8	0	0
T90	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	509821354	3812	0	0
TransStop_A	509821354	1955	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	3812	0	0
T1	241298	7	0	0
T2	139647	0	0	0
T3	0	17	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	10	0	0
T19	2104	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	6	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	9	0	0
T78	0	9	0	0
T90	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	1955	0	0
T1	241298	5	0	0
T2	139647	0	0	0
T3	0	9	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	5	0	0
T19	2104	0	0	0
T20	8693	4	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	5	0	0
T37	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T78	0	5	0	0
T90	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	509821354	3846	0	0
TransStop_A	509821354	1968	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	3846	0	0
T1	241298	8	0	0
T2	139647	0	0	0
T3	0	15	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	12	0	0
T19	2104	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	4	0	0
T37	0	1	0	0
T75	0	3	0	0
T76	0	10	0	0
T78	0	11	0	0
T90	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509821354	1968	0	0
T1	241298	7	0	0
T2	139647	0	0	0
T3	0	5	0	0
T4	33241	0	0	0
T5	72517	0	0	0
T12	0	6	0	0
T19	2104	0	0	0
T20	8693	3	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1553	0	0	0
T24	1429	0	0	0
T33	0	3	0	0
T37	0	1	0	0
T75	0	1	0	0
T76	0	6	0	0
T78	0	6	0	0
T90	0	5	0	0