Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	156129909	17992919	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	17992919	0	58
T1	231637	70983	0	1
T2	134055	24148	0	1
T3	0	109505	0	0
T4	32244	0	0	0
T5	35533	0	0	0
T12	0	23655	0	0
T13	0	9927	0	1
T14	0	781672	0	0
T15	0	6727	0	0
T16	0	6351	0	1
T17	0	0	0	1
T19	1010	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0
T25	0	940	0	1
T26	0	1037	0	1
T42	0	0	0	1
T59	0	0	0	1
T115	0	0	0	1