Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	157098638	5371666	0	0
clk_enables_rd_A	157098638	40685	0	0
clk_hints_rd_A	157098638	35342	0	0
extclk_ctrl_rd_A	157098638	44037	0	0
extclk_ctrl_regwen_rd_A	157098638	33840	0	0
jitter_enable_rd_A	157098638	51730	0	0
jitter_regwen_rd_A	157098638	38387	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	5371666	0	0
T3	103864	35089	0	0
T12	175766	0	0	0
T14	0	200065	0	0
T18	0	191032	0	0
T27	0	109537	0	0
T35	1567	0	0	0
T37	2201	0	0	0
T44	0	53573	0	0
T51	0	49453	0	0
T55	0	152095	0	0
T72	0	89058	0	0
T73	0	91493	0	0
T74	0	41341	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T79	1291	0	0	0
T80	1468	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	40685	0	0
T12	175766	0	0	0
T13	56566	0	0	0
T28	45107	0	0	0
T29	24173	0	0	0
T37	2201	4	0	0
T44	0	1257	0	0
T73	0	3746	0	0
T78	3085	0	0	0
T79	1291	0	0	0
T80	1468	0	0	0
T83	0	1	0	0
T90	1879	0	0	0
T91	1598	0	0	0
T137	0	4621	0	0
T138	0	3029	0	0
T139	0	9	0	0
T140	0	626	0	0
T141	0	2999	0	0
T142	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	35342	0	0
T12	175766	0	0	0
T13	56566	0	0	0
T28	45107	0	0	0
T29	24173	0	0	0
T37	2201	1	0	0
T44	0	1018	0	0
T73	0	3149	0	0
T78	3085	0	0	0
T79	1291	0	0	0
T80	1468	0	0	0
T83	0	3	0	0
T90	1879	0	0	0
T91	1598	0	0	0
T137	0	4534	0	0
T138	0	2422	0	0
T140	0	534	0	0
T141	0	2982	0	0
T142	0	3	0	0
T143	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	44037	0	0
T2	134055	0	0	0
T4	32244	37	0	0
T5	35533	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	2	0	0
T24	1357	0	0	0
T25	8890	0	0	0
T34	755	0	0	0
T44	0	1283	0	0
T45	0	61	0	0
T73	0	4015	0	0
T77	0	41	0	0
T79	0	28	0	0
T81	0	37	0	0
T92	0	7	0	0
T144	0	114	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	33840	0	0
T2	134055	0	0	0
T4	32244	9	0	0
T5	35533	0	0	0
T20	2085	0	0	0
T21	893	0	0	0
T22	1475	0	0	0
T23	1552	0	0	0
T24	1357	0	0	0
T25	8890	0	0	0
T34	755	0	0	0
T44	0	983	0	0
T73	0	3182	0	0
T137	0	4064	0	0
T138	0	2670	0	0
T140	0	549	0	0
T141	0	2637	0	0
T144	0	35	0	0
T145	0	20	0	0
T146	0	30	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	51730	0	0
T12	175766	0	0	0
T13	56566	0	0	0
T28	45107	0	0	0
T29	24173	0	0	0
T37	2201	121	0	0
T44	0	1072	0	0
T73	0	4294	0	0
T78	3085	0	0	0
T79	1291	0	0	0
T80	1468	0	0	0
T83	0	198	0	0
T90	1879	0	0	0
T91	1598	0	0	0
T137	0	6164	0	0
T138	0	3378	0	0
T139	0	110	0	0
T140	0	935	0	0
T141	0	4234	0	0
T143	0	116	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157098638	38387	0	0
T38	7605	0	0	0
T42	124181	0	0	0
T43	1912	0	0	0
T44	173540	1259	0	0
T45	1958	0	0	0
T46	988	0	0	0
T47	29277	0	0	0
T48	2100	0	0	0
T73	327320	3518	0	0
T137	0	4999	0	0
T138	0	2892	0	0
T140	0	752	0	0
T141	0	3200	0	0
T147	0	1618	0	0
T148	0	2001	0	0
T149	0	3454	0	0
T150	0	3661	0	0
T151	1419	0	0	0