Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T19

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 478978243 4645 0 0
g_div2.Div2Whole_A 478978243 5492 0 0
g_div4.Div4Stepped_A 239111664 4542 0 0
g_div4.Div4Whole_A 239111664 5191 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 478978243 4645 0 0
T1 231638 0 0 0
T2 134056 0 0 0
T3 0 16 0 0
T4 31910 0 0 0
T5 69614 0 0 0
T6 1830 4 0 0
T7 4225 0 0 0
T8 8763 4 0 0
T12 0 14 0 0
T19 2020 2 0 0
T20 8345 0 0 0
T21 3433 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 7 0 0
T79 0 5 0 0
T80 0 5 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 478978243 5492 0 0
T1 231638 0 0 0
T2 134056 0 0 0
T3 0 17 0 0
T4 31910 0 0 0
T5 69614 0 0 0
T6 1830 4 0 0
T7 4225 0 0 0
T8 8763 4 0 0
T12 0 14 0 0
T19 2020 2 0 0
T20 8345 0 0 0
T21 3433 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 8 0 0
T79 0 5 0 0
T80 0 5 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239111664 4542 0 0
T1 115711 0 0 0
T2 66988 0 0 0
T3 0 16 0 0
T4 10389 0 0 0
T5 18663 0 0 0
T6 932 4 0 0
T7 2093 0 0 0
T8 4761 4 0 0
T12 0 14 0 0
T19 1025 2 0 0
T20 4160 0 0 0
T21 1698 0 0 0
T22 0 3 0 0
T23 0 1 0 0
T77 0 7 0 0
T79 0 5 0 0
T80 0 5 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239111664 5191 0 0
T1 115711 0 0 0
T2 66988 0 0 0
T3 0 17 0 0
T4 10389 0 0 0
T5 18663 0 0 0
T6 932 4 0 0
T7 2093 0 0 0
T8 4761 4 0 0
T12 0 14 0 0
T19 1025 2 0 0
T20 4160 0 0 0
T21 1698 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 8 0 0
T79 0 5 0 0
T80 0 5 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T19

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 478978243 4645 0 0
g_div2.Div2Whole_A 478978243 5492 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 478978243 4645 0 0
T1 231638 0 0 0
T2 134056 0 0 0
T3 0 16 0 0
T4 31910 0 0 0
T5 69614 0 0 0
T6 1830 4 0 0
T7 4225 0 0 0
T8 8763 4 0 0
T12 0 14 0 0
T19 2020 2 0 0
T20 8345 0 0 0
T21 3433 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 7 0 0
T79 0 5 0 0
T80 0 5 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 478978243 5492 0 0
T1 231638 0 0 0
T2 134056 0 0 0
T3 0 17 0 0
T4 31910 0 0 0
T5 69614 0 0 0
T6 1830 4 0 0
T7 4225 0 0 0
T8 8763 4 0 0
T12 0 14 0 0
T19 2020 2 0 0
T20 8345 0 0 0
T21 3433 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 8 0 0
T79 0 5 0 0
T80 0 5 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T19

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 239111664 4542 0 0
g_div4.Div4Whole_A 239111664 5191 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239111664 4542 0 0
T1 115711 0 0 0
T2 66988 0 0 0
T3 0 16 0 0
T4 10389 0 0 0
T5 18663 0 0 0
T6 932 4 0 0
T7 2093 0 0 0
T8 4761 4 0 0
T12 0 14 0 0
T19 1025 2 0 0
T20 4160 0 0 0
T21 1698 0 0 0
T22 0 3 0 0
T23 0 1 0 0
T77 0 7 0 0
T79 0 5 0 0
T80 0 5 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239111664 5191 0 0
T1 115711 0 0 0
T2 66988 0 0 0
T3 0 17 0 0
T4 10389 0 0 0
T5 18663 0 0 0
T6 932 4 0 0
T7 2093 0 0 0
T8 4761 4 0 0
T12 0 14 0 0
T19 1025 2 0 0
T20 4160 0 0 0
T21 1698 0 0 0
T22 0 4 0 0
T23 0 1 0 0
T77 0 8 0 0
T79 0 5 0 0
T80 0 5 0 0

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