SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T8,T1 |
1 | 1 | Covered | T6,T8,T19 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 478978243 | 4645 | 0 | 0 |
g_div2.Div2Whole_A | 478978243 | 5492 | 0 | 0 |
g_div4.Div4Stepped_A | 239111664 | 4542 | 0 | 0 |
g_div4.Div4Whole_A | 239111664 | 5191 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 478978243 | 4645 | 0 | 0 |
T1 | 231638 | 0 | 0 | 0 |
T2 | 134056 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T4 | 31910 | 0 | 0 | 0 |
T5 | 69614 | 0 | 0 | 0 |
T6 | 1830 | 4 | 0 | 0 |
T7 | 4225 | 0 | 0 | 0 |
T8 | 8763 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 2020 | 2 | 0 | 0 |
T20 | 8345 | 0 | 0 | 0 |
T21 | 3433 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 7 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 478978243 | 5492 | 0 | 0 |
T1 | 231638 | 0 | 0 | 0 |
T2 | 134056 | 0 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T4 | 31910 | 0 | 0 | 0 |
T5 | 69614 | 0 | 0 | 0 |
T6 | 1830 | 4 | 0 | 0 |
T7 | 4225 | 0 | 0 | 0 |
T8 | 8763 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 2020 | 2 | 0 | 0 |
T20 | 8345 | 0 | 0 | 0 |
T21 | 3433 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239111664 | 4542 | 0 | 0 |
T1 | 115711 | 0 | 0 | 0 |
T2 | 66988 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T4 | 10389 | 0 | 0 | 0 |
T5 | 18663 | 0 | 0 | 0 |
T6 | 932 | 4 | 0 | 0 |
T7 | 2093 | 0 | 0 | 0 |
T8 | 4761 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 1025 | 2 | 0 | 0 |
T20 | 4160 | 0 | 0 | 0 |
T21 | 1698 | 0 | 0 | 0 |
T22 | 0 | 3 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 7 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239111664 | 5191 | 0 | 0 |
T1 | 115711 | 0 | 0 | 0 |
T2 | 66988 | 0 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T4 | 10389 | 0 | 0 | 0 |
T5 | 18663 | 0 | 0 | 0 |
T6 | 932 | 4 | 0 | 0 |
T7 | 2093 | 0 | 0 | 0 |
T8 | 4761 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 1025 | 2 | 0 | 0 |
T20 | 4160 | 0 | 0 | 0 |
T21 | 1698 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T8,T1 |
1 | 1 | Covered | T6,T8,T19 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 478978243 | 4645 | 0 | 0 |
g_div2.Div2Whole_A | 478978243 | 5492 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 478978243 | 4645 | 0 | 0 |
T1 | 231638 | 0 | 0 | 0 |
T2 | 134056 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T4 | 31910 | 0 | 0 | 0 |
T5 | 69614 | 0 | 0 | 0 |
T6 | 1830 | 4 | 0 | 0 |
T7 | 4225 | 0 | 0 | 0 |
T8 | 8763 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 2020 | 2 | 0 | 0 |
T20 | 8345 | 0 | 0 | 0 |
T21 | 3433 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 7 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 478978243 | 5492 | 0 | 0 |
T1 | 231638 | 0 | 0 | 0 |
T2 | 134056 | 0 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T4 | 31910 | 0 | 0 | 0 |
T5 | 69614 | 0 | 0 | 0 |
T6 | 1830 | 4 | 0 | 0 |
T7 | 4225 | 0 | 0 | 0 |
T8 | 8763 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 2020 | 2 | 0 | 0 |
T20 | 8345 | 0 | 0 | 0 |
T21 | 3433 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T8,T1 |
1 | 1 | Covered | T6,T8,T19 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 239111664 | 4542 | 0 | 0 |
g_div4.Div4Whole_A | 239111664 | 5191 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239111664 | 4542 | 0 | 0 |
T1 | 115711 | 0 | 0 | 0 |
T2 | 66988 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T4 | 10389 | 0 | 0 | 0 |
T5 | 18663 | 0 | 0 | 0 |
T6 | 932 | 4 | 0 | 0 |
T7 | 2093 | 0 | 0 | 0 |
T8 | 4761 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 1025 | 2 | 0 | 0 |
T20 | 4160 | 0 | 0 | 0 |
T21 | 1698 | 0 | 0 | 0 |
T22 | 0 | 3 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 7 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239111664 | 5191 | 0 | 0 |
T1 | 115711 | 0 | 0 | 0 |
T2 | 66988 | 0 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T4 | 10389 | 0 | 0 | 0 |
T5 | 18663 | 0 | 0 | 0 |
T6 | 932 | 4 | 0 | 0 |
T7 | 2093 | 0 | 0 | 0 |
T8 | 4761 | 4 | 0 | 0 |
T12 | 0 | 14 | 0 | 0 |
T19 | 1025 | 2 | 0 | 0 |
T20 | 4160 | 0 | 0 | 0 |
T21 | 1698 | 0 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T79 | 0 | 5 | 0 | 0 |
T80 | 0 | 5 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |