Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	468389727	438	0	0
StatusRise_A	468389727	438	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468389727	438	0	0
T3	311592	0	0	0
T12	527298	0	0	0
T33	7290	0	0	0
T34	2265	9	0	0
T35	4701	11	0	0
T36	0	13	0	0
T37	6603	0	0	0
T75	7164	0	0	0
T76	7686	0	0	0
T77	4917	0	0	0
T78	9255	0	0	0
T151	0	4	0	0
T152	0	17	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	3	0	0
T156	0	7	0	0
T157	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468389727	438	0	0
T3	311592	0	0	0
T12	527298	0	0	0
T33	7290	0	0	0
T34	2265	9	0	0
T35	4701	11	0	0
T36	0	13	0	0
T37	6603	0	0	0
T75	7164	0	0	0
T76	7686	0	0	0
T77	4917	0	0	0
T78	9255	0	0	0
T151	0	4	0	0
T152	0	17	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	3	0	0
T156	0	7	0	0
T157	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156129909	146	0	0
StatusRise_A	156129909	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	146	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	3	0	0
T36	0	4	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	146	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	3	0	0
T36	0	4	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156129909	144	0	0
StatusRise_A	156129909	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	144	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	4	0	0
T36	0	5	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	144	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	4	0	0
T36	0	5	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156129909	148	0	0
StatusRise_A	156129909	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	148	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	4	0	0
T36	0	4	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156129909	148	0	0
T3	103864	0	0	0
T12	175766	0	0	0
T33	2430	0	0	0
T34	755	3	0	0
T35	1567	4	0	0
T36	0	4	0	0
T37	2201	0	0	0
T75	2388	0	0	0
T76	2562	0	0	0
T77	1639	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	3	0	0