Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50426	0	0
CgEnOn_A	2147483647	41481	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50426	0	0
T1	646500	18	0	0
T2	374183	3	0	0
T3	2519682	15	0	0
T4	80734	18	0	0
T5	170124	33	0	0
T6	3225	3	0	0
T7	7363	3	0	0
T8	15904	3	0	0
T12	2247669	0	0	0
T18	0	5	0	0
T19	5659	3	0	0
T20	23277	8	0	0
T21	9554	3	0	0
T22	5675	0	0	0
T33	10769	5	0	0
T34	23842	18	0	0
T35	3343	23	0	0
T36	0	25	0	0
T37	4802	0	0	0
T44	0	5	0	0
T72	0	5	0	0
T75	5094	0	0	0
T76	10990	0	0	0
T77	27976	0	0	0
T78	6548	0	0	0
T151	0	10	0	0
T152	0	25	0	0
T153	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41481	0	0
T1	1486215	9	0	0
T2	860152	0	0	0
T3	3041676	134	0	0
T4	196409	0	0	0
T5	422480	0	0	0
T12	3017609	55	0	0
T14	0	478	0	0
T18	0	4	0	0
T19	12978	0	0	0
T20	53528	5	0	0
T21	21998	0	0	0
T22	35086	0	0	0
T23	9506	0	0	0
T24	8769	0	0	0
T33	23323	0	0	0
T34	53614	27	0	0
T35	7070	35	0	0
T36	0	25	0	0
T37	10372	4	0	0
T44	0	4	0	0
T72	0	5	0	0
T75	11075	0	0	0
T76	23700	0	0	0
T77	57029	0	0	0
T78	14199	0	0	0
T151	0	10	0	0
T152	0	25	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0
T158	0	15	0	0
T159	0	35	0	0
T160	0	35	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	239111273	152	0	0
CgEnOn_A	239111273	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111273	152	0	0
T3	932733	1	0	0
T12	499805	0	0	0
T18	0	1	0	0
T33	2363	0	0	0
T34	5281	3	0	0
T35	737	4	0	0
T36	0	5	0	0
T37	1059	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	1111	0	0	0
T76	2427	0	0	0
T77	6694	0	0	0
T78	1435	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111273	152	0	0
T3	932733	1	0	0
T12	499805	0	0	0
T18	0	1	0	0
T33	2363	0	0	0
T34	5281	3	0	0
T35	737	4	0	0
T36	0	5	0	0
T37	1059	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	1111	0	0	0
T76	2427	0	0	0
T77	6694	0	0	0
T78	1435	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	119554971	152	0	0
CgEnOn_A	119554971	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	119554971	152	0	0
CgEnOn_A	119554971	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	119554971	152	0	0
CgEnOn_A	119554971	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	152	0	0
T3	466365	1	0	0
T12	249901	0	0	0
T18	0	1	0	0
T33	1182	0	0	0
T34	2640	3	0	0
T35	369	4	0	0
T36	0	5	0	0
T37	529	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	556	0	0	0
T76	1214	0	0	0
T77	3345	0	0	0
T78	717	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	478977807	152	0	0
CgEnOn_A	478977807	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478977807	152	0	0
T3	187854	1	0	0
T12	998161	0	0	0
T18	0	1	0	0
T33	4860	0	0	0
T34	10641	3	0	0
T35	1499	4	0	0
T36	0	5	0	0
T37	2156	0	0	0
T44	0	1	0	0
T72	0	1	0	0
T75	2315	0	0	0
T76	4921	0	0	0
T77	11247	0	0	0
T78	2962	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478977807	148	0	0
T3	187854	0	0	0
T12	998161	0	0	0
T33	4860	0	0	0
T34	10641	3	0	0
T35	1499	4	0	0
T36	0	5	0	0
T37	2156	0	0	0
T72	0	1	0	0
T75	2315	0	0	0
T76	4921	0	0	0
T77	11247	0	0	0
T78	2962	0	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	148	0	0
CgEnOn_A	509820917	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	148	0	0
T3	210980	0	0	0
T12	112378	0	0	0
T14	0	2	0	0
T33	5062	0	0	0
T34	12018	3	0	0
T35	1505	3	0	0
T36	0	4	0	0
T37	2246	0	0	0
T75	2412	0	0	0
T76	5125	0	0	0
T77	11715	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	146	0	0
T3	210980	0	0	0
T12	112378	0	0	0
T33	5062	0	0	0
T34	12018	3	0	0
T35	1505	3	0	0
T36	0	4	0	0
T37	2246	0	0	0
T75	2412	0	0	0
T76	5125	0	0	0
T77	11715	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	148	0	0
CgEnOn_A	509820917	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	148	0	0
T3	210980	0	0	0
T12	112378	0	0	0
T14	0	2	0	0
T33	5062	0	0	0
T34	12018	3	0	0
T35	1505	3	0	0
T36	0	4	0	0
T37	2246	0	0	0
T75	2412	0	0	0
T76	5125	0	0	0
T77	11715	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	146	0	0
T3	210980	0	0	0
T12	112378	0	0	0
T33	5062	0	0	0
T34	12018	3	0	0
T35	1505	3	0	0
T36	0	4	0	0
T37	2246	0	0	0
T75	2412	0	0	0
T76	5125	0	0	0
T77	11715	0	0	0
T78	3085	0	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	244610269	153	0	0
CgEnOn_A	244610269	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610269	153	0	0
T3	100034	0	0	0
T12	545184	0	0	0
T18	0	1	0	0
T33	2430	0	0	0
T34	5736	3	0	0
T35	717	4	0	0
T36	0	4	0	0
T37	1078	0	0	0
T75	1157	0	0	0
T76	2460	0	0	0
T77	5623	0	0	0
T78	1481	0	0	0
T151	0	1	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610269	150	0	0
T3	100034	0	0	0
T12	545184	0	0	0
T33	2430	0	0	0
T34	5736	3	0	0
T35	717	4	0	0
T36	0	4	0	0
T37	1078	0	0	0
T75	1157	0	0	0
T76	2460	0	0	0
T77	5623	0	0	0
T78	1481	0	0	0
T151	0	1	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	119554971	8260	0	0
CgEnOn_A	119554971	6031	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	8260	0	0
T1	57855	4	0	0
T2	33494	1	0	0
T4	5196	6	0	0
T5	9332	11	0	0
T6	464	1	0	0
T7	1046	1	0	0
T8	2380	1	0	0
T19	512	1	0	0
T20	2080	1	0	0
T21	849	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119554971	6031	0	0
T1	57855	1	0	0
T2	33494	0	0	0
T3	0	39	0	0
T4	5196	0	0	0
T5	9332	0	0	0
T12	0	18	0	0
T14	0	150	0	0
T19	512	0	0	0
T20	2080	0	0	0
T21	849	0	0	0
T22	1404	0	0	0
T23	354	0	0	0
T24	333	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	5	0	0
T159	0	12	0	0
T160	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	239111273	8302	0	0
CgEnOn_A	239111273	6073	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111273	8302	0	0
T1	115711	4	0	0
T2	66988	1	0	0
T4	10389	6	0	0
T5	18662	11	0	0
T6	932	1	0	0
T7	2093	1	0	0
T8	4761	1	0	0
T19	1025	1	0	0
T20	4160	1	0	0
T21	1697	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239111273	6073	0	0
T1	115711	1	0	0
T2	66988	0	0	0
T3	0	41	0	0
T4	10389	0	0	0
T5	18662	0	0	0
T12	0	18	0	0
T14	0	161	0	0
T19	1025	0	0	0
T20	4160	0	0	0
T21	1697	0	0	0
T22	2810	0	0	0
T23	709	0	0	0
T24	667	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	5	0	0
T159	0	12	0	0
T160	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	478977807	8337	0	0
CgEnOn_A	478977807	6104	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478977807	8337	0	0
T1	231637	4	0	0
T2	134055	1	0	0
T4	31909	6	0	0
T5	69614	11	0	0
T6	1829	1	0	0
T7	4224	1	0	0
T8	8763	1	0	0
T19	2019	1	0	0
T20	8344	1	0	0
T21	3432	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478977807	6104	0	0
T1	231637	1	0	0
T2	134055	0	0	0
T3	0	40	0	0
T4	31909	0	0	0
T5	69614	0	0	0
T12	0	19	0	0
T14	0	167	0	0
T19	2019	0	0	0
T20	8344	0	0	0
T21	3432	0	0	0
T22	5448	0	0	0
T23	1491	0	0	0
T24	1371	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	5	0	0
T159	0	11	0	0
T160	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	244610269	8308	0	0
CgEnOn_A	244610269	6073	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610269	8308	0	0
T1	115824	4	0	0
T2	67031	1	0	0
T4	15955	6	0	0
T5	34808	11	0	0
T6	914	1	0	0
T7	2112	1	0	0
T8	4381	1	0	0
T19	1010	1	0	0
T20	4172	1	0	0
T21	1716	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244610269	6073	0	0
T1	115824	1	0	0
T2	67031	0	0	0
T3	0	41	0	0
T4	15955	0	0	0
T5	34808	0	0	0
T12	0	18	0	0
T14	0	160	0	0
T19	1010	0	0	0
T20	4172	0	0	0
T21	1716	0	0	0
T22	2724	0	0	0
T23	744	0	0	0
T24	686	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T158	0	5	0	0
T159	0	13	0	0
T160	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T20,T33
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	3976	0	0
CgEnOn_A	509820917	3974	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3976	0	0
T1	241297	6	0	0
T2	139646	0	0	0
T3	0	10	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	5	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	7	0	0
T78	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3974	0	0
T1	241297	6	0	0
T2	139646	0	0	0
T3	0	10	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	5	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	7	0	0
T78	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T20,T33
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	4080	0	0
CgEnOn_A	509820917	4078	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	4080	0	0
T1	241297	6	0	0
T2	139646	0	0	0
T3	0	19	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	6	0	0
T76	0	6	0	0
T78	0	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	4078	0	0
T1	241297	6	0	0
T2	139646	0	0	0
T3	0	19	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	6	0	0
T76	0	6	0	0
T78	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T20,T33
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	3960	0	0
CgEnOn_A	509820917	3958	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3960	0	0
T1	241297	7	0	0
T2	139646	0	0	0
T3	0	17	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	6	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	9	0	0
T78	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3958	0	0
T1	241297	7	0	0
T2	139646	0	0	0
T3	0	17	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	6	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	4	0	0
T76	0	9	0	0
T78	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T20,T33
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	509820917	3994	0	0
CgEnOn_A	509820917	3992	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3994	0	0
T1	241297	8	0	0
T2	139646	0	0	0
T3	0	15	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	3	0	0
T76	0	10	0	0
T78	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509820917	3992	0	0
T1	241297	8	0	0
T2	139646	0	0	0
T3	0	15	0	0
T4	33240	0	0	0
T5	72516	0	0	0
T19	2103	0	0	0
T20	8693	5	0	0
T21	3576	0	0	0
T22	5675	0	0	0
T23	1552	0	0	0
T24	1428	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T75	0	3	0	0
T76	0	10	0	0
T78	0	11	0	0