Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3736359

1

T5

74

T6

17

T7

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1069808	1			T5	6		T6	28		T7	16
values[0x0]	1520236	1			T5	68		T6	19		T7	18
values[0x1]	1787585	1			T5	59		T6	20		T7	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4026354

1

T5

87

T6

22

T7

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16977	1			T5	1		T1	10		T3	249
valid_sources[0x01]	18006	1			T23	3		T1	3		T3	286
valid_sources[0x02]	16735	1			T5	2		T1	5		T4	13
valid_sources[0x03]	16755	1			T22	3		T1	3		T3	268
valid_sources[0x04]	17353	1			T6	6		T22	2		T1	2
valid_sources[0x05]	17100	1			T1	3		T3	284		T8	1
valid_sources[0x06]	18195	1			T5	2		T1	7		T4	1
valid_sources[0x07]	18437	1			T5	1		T1	2		T2	6
valid_sources[0x08]	16922	1			T7	1		T1	8		T4	8
valid_sources[0x09]	17306	1			T7	1		T1	4		T3	294
valid_sources[0x0a]	17282	1			T1	3		T2	12		T4	1
valid_sources[0x0b]	17092	1			T5	1		T7	1		T1	7
valid_sources[0x0c]	18031	1			T5	1		T22	1		T1	4
valid_sources[0x0d]	18492	1			T5	2		T1	1		T3	294
valid_sources[0x0e]	18346	1			T5	1		T1	3		T3	279
valid_sources[0x0f]	16294	1			T5	1		T1	7		T2	4
valid_sources[0x10]	17674	1			T7	1		T1	2		T2	10
valid_sources[0x11]	18202	1			T5	1		T6	1		T1	7
valid_sources[0x12]	17371	1			T5	1		T1	9		T3	304
valid_sources[0x13]	17300	1			T5	1		T1	7		T3	257
valid_sources[0x14]	17435	1			T7	1		T1	3		T4	1
valid_sources[0x15]	16705	1			T1	7		T4	15		T3	215
valid_sources[0x16]	16547	1			T5	1		T1	5		T4	3
valid_sources[0x17]	16211	1			T5	4		T1	5		T4	7
valid_sources[0x18]	15890	1			T5	1		T22	1		T4	3
valid_sources[0x19]	16471	1			T1	5		T4	9		T3	267
valid_sources[0x1a]	17772	1			T7	1		T1	4		T3	279
valid_sources[0x1b]	17768	1			T6	1		T7	2		T1	9
valid_sources[0x1c]	19317	1			T5	1		T1	2		T15	119
valid_sources[0x1d]	17843	1			T5	1		T1	8		T4	7
valid_sources[0x1e]	15690	1			T1	3		T2	3		T4	1
valid_sources[0x1f]	18545	1			T5	1		T1	5		T2	4
valid_sources[0x20]	18536	1			T5	1		T1	7		T4	1
valid_sources[0x21]	16650	1			T1	6		T4	13		T3	336
valid_sources[0x22]	16693	1			T1	4		T2	6		T3	219
valid_sources[0x23]	16940	1			T1	4		T4	10		T3	224
valid_sources[0x24]	17334	1			T5	2		T1	6		T3	278
valid_sources[0x25]	17033	1			T5	1		T1	4		T4	2
valid_sources[0x26]	16537	1			T5	1		T7	1		T22	3
valid_sources[0x27]	17563	1			T7	1		T22	2		T1	4
valid_sources[0x28]	17435	1			T1	6		T4	14		T3	278
valid_sources[0x29]	16444	1			T5	1		T1	5		T4	1
valid_sources[0x2a]	18759	1			T1	9		T4	2		T3	245
valid_sources[0x2b]	16804	1			T1	9		T3	203		T86	1
valid_sources[0x2c]	16260	1			T5	2		T1	7		T4	9
valid_sources[0x2d]	16447	1			T6	1		T1	13		T4	3
valid_sources[0x2e]	16841	1			T1	4		T3	256		T19	2
valid_sources[0x2f]	16766	1			T1	4		T4	1		T3	217
valid_sources[0x30]	15135	1			T7	1		T1	3		T2	5
valid_sources[0x31]	17440	1			T1	7		T4	1		T3	297
valid_sources[0x32]	17636	1			T1	3		T4	2		T3	366
valid_sources[0x33]	16528	1			T23	1		T1	6		T2	1
valid_sources[0x34]	16407	1			T5	2		T7	1		T1	6
valid_sources[0x35]	17215	1			T4	1		T3	280		T11	2
valid_sources[0x36]	18501	1			T1	4		T3	327		T19	1
valid_sources[0x37]	17164	1			T1	3		T4	1		T3	334
valid_sources[0x38]	16777	1			T5	1		T1	10		T3	280
valid_sources[0x39]	18544	1			T6	4		T23	1		T1	3
valid_sources[0x3a]	17598	1			T5	1		T1	6		T3	307
valid_sources[0x3b]	16758	1			T5	1		T1	8		T2	6
valid_sources[0x3c]	17244	1			T5	3		T22	1		T1	3
valid_sources[0x3d]	16980	1			T6	9		T7	1		T1	6
valid_sources[0x3e]	19198	1			T7	1		T1	12		T3	266
valid_sources[0x3f]	17083	1			T1	3		T3	284		T9	35
valid_sources[0x40]	17389	1			T1	12		T2	6		T4	2
valid_sources[0x41]	16768	1			T1	10		T4	3		T3	261
valid_sources[0x42]	17162	1			T1	12		T4	3		T3	285
valid_sources[0x43]	16362	1			T1	7		T4	2		T3	304
valid_sources[0x44]	16687	1			T23	5		T1	7		T4	3
valid_sources[0x45]	16287	1			T22	2		T1	7		T2	1
valid_sources[0x46]	17163	1			T1	7		T3	300		T19	3
valid_sources[0x47]	16814	1			T5	2		T1	4		T4	1
valid_sources[0x48]	17663	1			T5	1		T1	3		T4	4
valid_sources[0x49]	17348	1			T1	6		T3	222		T11	1
valid_sources[0x4a]	16111	1			T5	1		T6	1		T1	7
valid_sources[0x4b]	17575	1			T5	1		T22	2		T1	2
valid_sources[0x4c]	16269	1			T6	2		T1	2		T4	10
valid_sources[0x4d]	16837	1			T1	5		T2	6		T4	4
valid_sources[0x4e]	16843	1			T1	4		T4	4		T3	318
valid_sources[0x4f]	15577	1			T23	2		T1	3		T2	12
valid_sources[0x50]	18050	1			T1	5		T3	279		T19	2
valid_sources[0x51]	17052	1			T1	4		T2	3		T4	3
valid_sources[0x52]	20150	1			T6	3		T23	1		T1	7
valid_sources[0x53]	16685	1			T5	1		T1	2		T4	6
valid_sources[0x54]	16897	1			T5	1		T1	2		T4	2
valid_sources[0x55]	16942	1			T5	2		T1	2		T2	3
valid_sources[0x56]	17196	1			T22	1		T1	6		T4	2
valid_sources[0x57]	16836	1			T5	1		T7	1		T1	5
valid_sources[0x58]	17675	1			T23	2		T1	7		T3	301
valid_sources[0x59]	17183	1			T1	3		T2	3		T4	1
valid_sources[0x5a]	15882	1			T1	1		T4	4		T3	269
valid_sources[0x5b]	17426	1			T5	1		T23	1		T1	3
valid_sources[0x5c]	15929	1			T5	2		T1	3		T4	5
valid_sources[0x5d]	18257	1			T5	1		T1	7		T3	361
valid_sources[0x5e]	17840	1			T22	1		T1	10		T3	303
valid_sources[0x5f]	16984	1			T1	3		T2	2		T4	5
valid_sources[0x60]	17294	1			T5	1		T7	1		T1	7
valid_sources[0x61]	16215	1			T5	1		T22	8		T1	4
valid_sources[0x62]	17419	1			T23	1		T1	2		T2	4
valid_sources[0x63]	16283	1			T7	1		T1	12		T4	4
valid_sources[0x64]	17034	1			T1	6		T3	244		T74	1
valid_sources[0x65]	17202	1			T5	1		T1	2		T2	3
valid_sources[0x66]	18670	1			T5	2		T1	4		T4	1
valid_sources[0x67]	15943	1			T6	1		T1	7		T4	4
valid_sources[0x68]	17412	1			T5	1		T1	7		T2	17
valid_sources[0x69]	17774	1			T5	2		T1	7		T4	5
valid_sources[0x6a]	15591	1			T5	1		T1	2		T4	1
valid_sources[0x6b]	16056	1			T1	6		T2	2		T3	297
valid_sources[0x6c]	15821	1			T5	1		T7	3		T23	4
valid_sources[0x6d]	17238	1			T1	7		T3	293		T19	4
valid_sources[0x6e]	17872	1			T5	1		T1	5		T2	6
valid_sources[0x6f]	17420	1			T5	1		T1	4		T4	6
valid_sources[0x70]	16932	1			T1	10		T3	330		T8	2
valid_sources[0x71]	16114	1			T1	1		T4	4		T3	258
valid_sources[0x72]	16879	1			T22	1		T1	3		T3	271
valid_sources[0x73]	15966	1			T5	2		T1	6		T2	17
valid_sources[0x74]	16870	1			T1	2		T2	1		T3	267
valid_sources[0x75]	17447	1			T23	1		T1	4		T4	2
valid_sources[0x76]	16458	1			T1	8		T4	2		T3	263
valid_sources[0x77]	17352	1			T7	1		T1	3		T4	3
valid_sources[0x78]	16724	1			T1	9		T2	5		T3	245
valid_sources[0x79]	19520	1			T5	2		T1	4		T4	1
valid_sources[0x7a]	17828	1			T1	3		T2	7		T4	6
valid_sources[0x7b]	17282	1			T1	3		T4	2		T3	289
valid_sources[0x7c]	16692	1			T5	1		T1	3		T4	3
valid_sources[0x7d]	16838	1			T1	3		T4	2		T3	320
valid_sources[0x7e]	16596	1			T5	1		T6	3		T1	4
valid_sources[0x7f]	17516	1			T22	3		T1	6		T4	17
valid_sources[0x80]	17348	1			T1	6		T4	6		T3	260

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

940320

1

T5

5

T6

14

T7

11

values[0x0]

all_enables

biggest_size

1422908

1

T5

47

T6

1

T7

9

values[0x1]

all_enables

biggest_size

1373131

1

T5

22

T6

2

T7

1