SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[clkmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 12065934 | 0 | T5 | 133 | T6 | 67 | T7 | 49 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 12065755 | 1 | T5 | 133 | T6 | 67 | T7 | 49 | ||||
values[1] | 11 | 1 | T94 | 2 | T99 | 1 | T100 | 1 | ||||
values[2] | 3 | 1 | T103 | 1 | T159 | 1 | T160 | 1 | ||||
values[3] | 92 | 1 | T94 | 10 | T95 | 3 | T96 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 12065773 | 1 | T5 | 133 | T6 | 67 | T7 | 49 | ||||
values[1] | 16 | 1 | T94 | 1 | T96 | 1 | T99 | 1 | ||||
values[2] | 5 | 1 | T96 | 1 | T102 | 1 | T161 | 1 | ||||
values[3] | 82 | 1 | T94 | 6 | T95 | 3 | T96 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 12065684 | 1 | T5 | 133 | T6 | 67 | T7 | 49 | ||||
auto[TlIntgErrCmd] | 89 | 1 | T94 | 7 | T95 | 3 | T96 | 6 | ||||
auto[TlIntgErrData] | 71 | 1 | T94 | 3 | T95 | 2 | T96 | 6 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T94 | 10 | T95 | 5 | T96 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |