Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T1
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T4
1	0	Covered	T25,T16,T17
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1125040295	13299	0	0
GateOpen_A	1125040295	19516	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1125040295	13299	0	0
T1	887427	9	0	0
T2	315310	0	0	0
T3	0	169	0	0
T12	0	108	0	0
T13	0	298	0	0
T15	19437	0	0	0
T16	8438	14	0	0
T17	3448	8	0	0
T21	5018	4	0	0
T22	16852	0	0	0
T23	3826	0	0	0
T24	63134	0	0	0
T25	2905	11	0	0
T74	0	4	0	0
T158	0	16	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1125040295	19516	0	0
T1	887427	29	0	0
T2	315310	0	0	0
T4	0	60	0	0
T7	9137	4	0	0
T15	19437	4	0	0
T16	8438	18	0	0
T17	0	12	0	0
T21	5018	4	0	0
T22	16852	4	0	0
T23	3826	0	0	0
T24	63134	4	0	0
T25	2905	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T1
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T4
1	0	Covered	T25,T16,T17
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	124386272	3176	0	0
GateOpen_A	124386272	4729	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124386272	3176	0	0
T1	95644	1	0	0
T2	35026	0	0	0
T3	0	40	0	0
T12	0	28	0	0
T13	0	74	0	0
T15	2147	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T21	542	1	0	0
T22	1998	0	0	0
T23	419	0	0	0
T24	7364	0	0	0
T25	318	3	0	0
T74	0	1	0	0
T158	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124386272	4729	0	0
T1	95644	6	0	0
T2	35026	0	0	0
T4	0	15	0	0
T7	1071	1	0	0
T15	2147	1	0	0
T16	924	5	0	0
T17	0	3	0	0
T21	542	1	0	0
T22	1998	1	0	0
T23	419	0	0	0
T24	7364	1	0	0
T25	318	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T1
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T4
1	0	Covered	T25,T16,T17
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	248773328	3390	0	0
GateOpen_A	248773328	4943	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248773328	3390	0	0
T1	191286	3	0	0
T2	70051	0	0	0
T3	0	44	0	0
T12	0	26	0	0
T13	0	75	0	0
T15	4293	0	0	0
T16	1848	4	0	0
T17	720	2	0	0
T21	1084	1	0	0
T22	4000	0	0	0
T23	837	0	0	0
T24	14729	0	0	0
T25	635	3	0	0
T74	0	1	0	0
T158	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248773328	4943	0	0
T1	191286	8	0	0
T2	70051	0	0	0
T4	0	15	0	0
T7	2142	1	0	0
T15	4293	1	0	0
T16	1848	5	0	0
T17	0	3	0	0
T21	1084	1	0	0
T22	4000	1	0	0
T23	837	0	0	0
T24	14729	1	0	0
T25	635	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T1
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T4
1	0	Covered	T25,T16,T17
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	497177688	3359	0	0
GateOpen_A	497177688	4915	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177688	3359	0	0
T1	383045	4	0	0
T2	140153	0	0	0
T3	0	43	0	0
T12	0	26	0	0
T13	0	72	0	0
T15	8665	0	0	0
T16	3733	4	0	0
T17	1574	2	0	0
T21	2262	1	0	0
T22	7236	0	0	0
T23	1713	0	0	0
T24	27360	0	0	0
T25	1335	3	0	0
T74	0	1	0	0
T158	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177688	4915	0	0
T1	383045	9	0	0
T2	140153	0	0	0
T4	0	15	0	0
T7	3949	1	0	0
T15	8665	1	0	0
T16	3733	5	0	0
T17	0	3	0	0
T21	2262	1	0	0
T22	7236	1	0	0
T23	1713	0	0	0
T24	27360	1	0	0
T25	1335	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T1
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T4
1	0	Covered	T25,T16,T17
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	254703007	3374	0	0
GateOpen_A	254703007	4929	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254703007	3374	0	0
T1	217452	1	0	0
T2	70080	0	0	0
T3	0	42	0	0
T12	0	28	0	0
T13	0	77	0	0
T15	4332	0	0	0
T16	1933	2	0	0
T17	794	2	0	0
T21	1130	1	0	0
T22	3618	0	0	0
T23	857	0	0	0
T24	13681	0	0	0
T25	617	2	0	0
T74	0	1	0	0
T158	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254703007	4929	0	0
T1	217452	6	0	0
T2	70080	0	0	0
T4	0	15	0	0
T7	1975	1	0	0
T15	4332	1	0	0
T16	1933	3	0	0
T17	0	3	0	0
T21	1130	1	0	0
T22	3618	1	0	0
T23	857	0	0	0
T24	13681	1	0	0
T25	617	3	0	0