Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	792727385	74922	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792727385	74922	0	0
T1	2203210	115	0	0
T2	175190	133	0	0
T3	1623960	1031	0	0
T4	128175	0	0	0
T8	0	55	0	0
T9	0	228	0	0
T10	0	92	0	0
T11	0	405	0	0
T12	0	871	0	0
T13	0	2254	0	0
T14	0	1199	0	0
T15	11280	0	0	0
T16	5370	0	0	0
T17	8170	0	0	0
T18	5020	0	0	0
T19	14445	0	0	0
T20	7705	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158545477	11161	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	11161	0	0
T1	440642	17	0	0
T2	35038	21	0	0
T3	324792	152	0	0
T4	25635	0	0	0
T8	0	9	0	0
T9	0	29	0	0
T10	0	12	0	0
T11	0	59	0	0
T12	0	140	0	0
T13	0	319	0	0
T14	0	154	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158545477	10983	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	10983	0	0
T1	440642	15	0	0
T2	35038	21	0	0
T3	324792	129	0	0
T4	25635	0	0	0
T8	0	9	0	0
T9	0	33	0	0
T10	0	13	0	0
T11	0	51	0	0
T12	0	138	0	0
T13	0	314	0	0
T14	0	174	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158545477	15183	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	15183	0	0
T1	440642	23	0	0
T2	35038	27	0	0
T3	324792	202	0	0
T4	25635	0	0	0
T8	0	11	0	0
T9	0	45	0	0
T10	0	18	0	0
T11	0	81	0	0
T12	0	177	0	0
T13	0	504	0	0
T14	0	236	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158545477	15019	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	15019	0	0
T1	440642	23	0	0
T2	35038	27	0	0
T3	324792	207	0	0
T4	25635	0	0	0
T8	0	11	0	0
T9	0	45	0	0
T10	0	17	0	0
T11	0	83	0	0
T12	0	176	0	0
T13	0	438	0	0
T14	0	237	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158545477	22576	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	22576	0	0
T1	440642	37	0	0
T2	35038	37	0	0
T3	324792	341	0	0
T4	25635	0	0	0
T8	0	15	0	0
T9	0	76	0	0
T10	0	32	0	0
T11	0	131	0	0
T12	0	240	0	0
T13	0	679	0	0
T14	0	398	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0