Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
T23 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11354610 |
11327261 |
0 |
0 |
T2 |
2259967 |
2258824 |
0 |
0 |
T5 |
1039321 |
1036898 |
0 |
0 |
T6 |
66006 |
59866 |
0 |
0 |
T7 |
74263 |
72307 |
0 |
0 |
T21 |
60472 |
55465 |
0 |
0 |
T22 |
118280 |
115260 |
0 |
0 |
T23 |
46063 |
42141 |
0 |
0 |
T24 |
370927 |
367950 |
0 |
0 |
T25 |
37058 |
33354 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
951272862 |
937264284 |
0 |
14490 |
T1 |
2643852 |
2636994 |
0 |
18 |
T2 |
210228 |
210096 |
0 |
18 |
T5 |
107868 |
107586 |
0 |
18 |
T6 |
15132 |
13590 |
0 |
18 |
T7 |
10356 |
10026 |
0 |
18 |
T21 |
13710 |
12462 |
0 |
18 |
T22 |
11298 |
10944 |
0 |
18 |
T23 |
10488 |
9480 |
0 |
18 |
T24 |
10254 |
10140 |
0 |
18 |
T25 |
8712 |
7770 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
3004396 |
2996195 |
0 |
21 |
T2 |
794217 |
793746 |
0 |
21 |
T5 |
360473 |
359457 |
0 |
21 |
T6 |
17554 |
15764 |
0 |
21 |
T7 |
23852 |
23102 |
0 |
21 |
T21 |
16255 |
14773 |
0 |
21 |
T22 |
41149 |
39891 |
0 |
21 |
T23 |
12344 |
11155 |
0 |
21 |
T24 |
144782 |
143395 |
0 |
21 |
T25 |
9791 |
8698 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
194465 |
0 |
0 |
T1 |
3004396 |
311 |
0 |
0 |
T2 |
794217 |
4 |
0 |
0 |
T3 |
0 |
919 |
0 |
0 |
T5 |
275644 |
4 |
0 |
0 |
T6 |
17554 |
222 |
0 |
0 |
T7 |
23852 |
139 |
0 |
0 |
T12 |
0 |
155 |
0 |
0 |
T15 |
13176 |
0 |
0 |
0 |
T18 |
0 |
35 |
0 |
0 |
T20 |
0 |
59 |
0 |
0 |
T21 |
16255 |
16 |
0 |
0 |
T22 |
41149 |
261 |
0 |
0 |
T23 |
12344 |
12 |
0 |
0 |
T24 |
144782 |
111 |
0 |
0 |
T25 |
9791 |
38 |
0 |
0 |
T72 |
0 |
7 |
0 |
0 |
T73 |
0 |
7 |
0 |
0 |
T86 |
0 |
60 |
0 |
0 |
T107 |
0 |
42 |
0 |
0 |
T108 |
0 |
3 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5706362 |
5693760 |
0 |
0 |
T2 |
1255522 |
1254943 |
0 |
0 |
T5 |
570980 |
569816 |
0 |
0 |
T6 |
33320 |
30473 |
0 |
0 |
T7 |
40055 |
39140 |
0 |
0 |
T21 |
30507 |
28191 |
0 |
0 |
T22 |
65833 |
64386 |
0 |
0 |
T23 |
23231 |
21467 |
0 |
0 |
T24 |
215891 |
214376 |
0 |
0 |
T25 |
18555 |
16847 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
497177267 |
493367200 |
0 |
0 |
T1 |
383044 |
381925 |
0 |
0 |
T2 |
140153 |
140073 |
0 |
0 |
T5 |
48873 |
48698 |
0 |
0 |
T6 |
2422 |
2177 |
0 |
0 |
T7 |
3948 |
3827 |
0 |
0 |
T21 |
2261 |
2058 |
0 |
0 |
T22 |
7235 |
7018 |
0 |
0 |
T23 |
1712 |
1550 |
0 |
0 |
T24 |
27360 |
27102 |
0 |
0 |
T25 |
1335 |
1187 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
497177267 |
493360587 |
0 |
2415 |
T1 |
383044 |
381901 |
0 |
3 |
T2 |
140153 |
140070 |
0 |
3 |
T5 |
48873 |
48695 |
0 |
3 |
T6 |
2422 |
2174 |
0 |
3 |
T7 |
3948 |
3824 |
0 |
3 |
T21 |
2261 |
2055 |
0 |
3 |
T22 |
7235 |
7015 |
0 |
3 |
T23 |
1712 |
1547 |
0 |
3 |
T24 |
27360 |
27099 |
0 |
3 |
T25 |
1335 |
1184 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
497177267 |
27540 |
0 |
0 |
T1 |
383044 |
0 |
0 |
0 |
T2 |
140153 |
0 |
0 |
0 |
T3 |
0 |
388 |
0 |
0 |
T6 |
2422 |
46 |
0 |
0 |
T7 |
3948 |
33 |
0 |
0 |
T15 |
8664 |
0 |
0 |
0 |
T18 |
0 |
10 |
0 |
0 |
T20 |
0 |
26 |
0 |
0 |
T21 |
2261 |
0 |
0 |
0 |
T22 |
7235 |
106 |
0 |
0 |
T23 |
1712 |
0 |
0 |
0 |
T24 |
27360 |
32 |
0 |
0 |
T25 |
1335 |
0 |
0 |
0 |
T72 |
0 |
3 |
0 |
0 |
T73 |
0 |
3 |
0 |
0 |
T107 |
0 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
17186 |
0 |
0 |
T1 |
440642 |
0 |
0 |
0 |
T2 |
35038 |
0 |
0 |
0 |
T3 |
0 |
232 |
0 |
0 |
T6 |
2522 |
50 |
0 |
0 |
T7 |
1726 |
3 |
0 |
0 |
T12 |
0 |
155 |
0 |
0 |
T15 |
2256 |
0 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T21 |
2285 |
0 |
0 |
0 |
T22 |
1883 |
42 |
0 |
0 |
T23 |
1748 |
0 |
0 |
0 |
T24 |
1709 |
19 |
0 |
0 |
T25 |
1452 |
0 |
0 |
0 |
T72 |
0 |
3 |
0 |
0 |
T86 |
0 |
60 |
0 |
0 |
T108 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T22 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T22 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
19522 |
0 |
0 |
T1 |
440642 |
0 |
0 |
0 |
T2 |
35038 |
0 |
0 |
0 |
T3 |
0 |
299 |
0 |
0 |
T6 |
2522 |
46 |
0 |
0 |
T7 |
1726 |
36 |
0 |
0 |
T15 |
2256 |
0 |
0 |
0 |
T18 |
0 |
7 |
0 |
0 |
T20 |
0 |
33 |
0 |
0 |
T21 |
2285 |
0 |
0 |
0 |
T22 |
1883 |
33 |
0 |
0 |
T23 |
1748 |
0 |
0 |
0 |
T24 |
1709 |
14 |
0 |
0 |
T25 |
1452 |
0 |
0 |
0 |
T72 |
0 |
1 |
0 |
0 |
T73 |
0 |
4 |
0 |
0 |
T107 |
0 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
528490352 |
0 |
0 |
T1 |
435017 |
434519 |
0 |
0 |
T2 |
145997 |
145942 |
0 |
0 |
T5 |
68911 |
68842 |
0 |
0 |
T6 |
2522 |
2396 |
0 |
0 |
T7 |
4113 |
4072 |
0 |
0 |
T21 |
2356 |
2258 |
0 |
0 |
T22 |
7537 |
7453 |
0 |
0 |
T23 |
1784 |
1744 |
0 |
0 |
T24 |
28501 |
28360 |
0 |
0 |
T25 |
1388 |
1319 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
528490352 |
0 |
0 |
T1 |
435017 |
434519 |
0 |
0 |
T2 |
145997 |
145942 |
0 |
0 |
T5 |
68911 |
68842 |
0 |
0 |
T6 |
2522 |
2396 |
0 |
0 |
T7 |
4113 |
4072 |
0 |
0 |
T21 |
2356 |
2258 |
0 |
0 |
T22 |
7537 |
7453 |
0 |
0 |
T23 |
1784 |
1744 |
0 |
0 |
T24 |
28501 |
28360 |
0 |
0 |
T25 |
1388 |
1319 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
497177267 |
495263651 |
0 |
0 |
T1 |
383044 |
382569 |
0 |
0 |
T2 |
140153 |
140101 |
0 |
0 |
T5 |
48873 |
48807 |
0 |
0 |
T6 |
2422 |
2301 |
0 |
0 |
T7 |
3948 |
3909 |
0 |
0 |
T21 |
2261 |
2167 |
0 |
0 |
T22 |
7235 |
7155 |
0 |
0 |
T23 |
1712 |
1673 |
0 |
0 |
T24 |
27360 |
27225 |
0 |
0 |
T25 |
1335 |
1269 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
497177267 |
495263651 |
0 |
0 |
T1 |
383044 |
382569 |
0 |
0 |
T2 |
140153 |
140101 |
0 |
0 |
T5 |
48873 |
48807 |
0 |
0 |
T6 |
2422 |
2301 |
0 |
0 |
T7 |
3948 |
3909 |
0 |
0 |
T21 |
2261 |
2167 |
0 |
0 |
T22 |
7235 |
7155 |
0 |
0 |
T23 |
1712 |
1673 |
0 |
0 |
T24 |
27360 |
27225 |
0 |
0 |
T25 |
1335 |
1269 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
248772914 |
248772914 |
0 |
0 |
T1 |
191286 |
191286 |
0 |
0 |
T2 |
70051 |
70051 |
0 |
0 |
T5 |
24404 |
24404 |
0 |
0 |
T6 |
1298 |
1298 |
0 |
0 |
T7 |
2142 |
2142 |
0 |
0 |
T21 |
1084 |
1084 |
0 |
0 |
T22 |
4000 |
4000 |
0 |
0 |
T23 |
837 |
837 |
0 |
0 |
T24 |
14729 |
14729 |
0 |
0 |
T25 |
635 |
635 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
248772914 |
248772914 |
0 |
0 |
T1 |
191286 |
191286 |
0 |
0 |
T2 |
70051 |
70051 |
0 |
0 |
T5 |
24404 |
24404 |
0 |
0 |
T6 |
1298 |
1298 |
0 |
0 |
T7 |
2142 |
2142 |
0 |
0 |
T21 |
1084 |
1084 |
0 |
0 |
T22 |
4000 |
4000 |
0 |
0 |
T23 |
837 |
837 |
0 |
0 |
T24 |
14729 |
14729 |
0 |
0 |
T25 |
635 |
635 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124385862 |
124385862 |
0 |
0 |
T1 |
95643 |
95643 |
0 |
0 |
T2 |
35025 |
35025 |
0 |
0 |
T5 |
12202 |
12202 |
0 |
0 |
T6 |
648 |
648 |
0 |
0 |
T7 |
1070 |
1070 |
0 |
0 |
T21 |
542 |
542 |
0 |
0 |
T22 |
1998 |
1998 |
0 |
0 |
T23 |
418 |
418 |
0 |
0 |
T24 |
7363 |
7363 |
0 |
0 |
T25 |
317 |
317 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124385862 |
124385862 |
0 |
0 |
T1 |
95643 |
95643 |
0 |
0 |
T2 |
35025 |
35025 |
0 |
0 |
T5 |
12202 |
12202 |
0 |
0 |
T6 |
648 |
648 |
0 |
0 |
T7 |
1070 |
1070 |
0 |
0 |
T21 |
542 |
542 |
0 |
0 |
T22 |
1998 |
1998 |
0 |
0 |
T23 |
418 |
418 |
0 |
0 |
T24 |
7363 |
7363 |
0 |
0 |
T25 |
317 |
317 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
254702600 |
253731847 |
0 |
0 |
T1 |
217452 |
217213 |
0 |
0 |
T2 |
70080 |
70054 |
0 |
0 |
T5 |
33078 |
33045 |
0 |
0 |
T6 |
1210 |
1150 |
0 |
0 |
T7 |
1974 |
1955 |
0 |
0 |
T21 |
1130 |
1084 |
0 |
0 |
T22 |
3617 |
3578 |
0 |
0 |
T23 |
856 |
837 |
0 |
0 |
T24 |
13680 |
13613 |
0 |
0 |
T25 |
616 |
583 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
254702600 |
253731847 |
0 |
0 |
T1 |
217452 |
217213 |
0 |
0 |
T2 |
70080 |
70054 |
0 |
0 |
T5 |
33078 |
33045 |
0 |
0 |
T6 |
1210 |
1150 |
0 |
0 |
T7 |
1974 |
1955 |
0 |
0 |
T21 |
1130 |
1084 |
0 |
0 |
T22 |
3617 |
3578 |
0 |
0 |
T23 |
856 |
837 |
0 |
0 |
T24 |
13680 |
13613 |
0 |
0 |
T25 |
616 |
583 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156210714 |
0 |
2415 |
T1 |
440642 |
439499 |
0 |
3 |
T2 |
35038 |
35016 |
0 |
3 |
T5 |
17978 |
17931 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
1726 |
1671 |
0 |
3 |
T21 |
2285 |
2077 |
0 |
3 |
T22 |
1883 |
1824 |
0 |
3 |
T23 |
1748 |
1580 |
0 |
3 |
T24 |
1709 |
1690 |
0 |
3 |
T25 |
1452 |
1295 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
158545477 |
156217442 |
0 |
0 |
T1 |
440642 |
439523 |
0 |
0 |
T2 |
35038 |
35019 |
0 |
0 |
T5 |
17978 |
17934 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
1726 |
1674 |
0 |
0 |
T21 |
2285 |
2080 |
0 |
0 |
T22 |
1883 |
1827 |
0 |
0 |
T23 |
1748 |
1583 |
0 |
0 |
T24 |
1709 |
1693 |
0 |
0 |
T25 |
1452 |
1298 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526461095 |
0 |
2415 |
T1 |
435017 |
433824 |
0 |
3 |
T2 |
145997 |
145911 |
0 |
3 |
T5 |
68911 |
68725 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
4113 |
3984 |
0 |
3 |
T21 |
2356 |
2141 |
0 |
3 |
T22 |
7537 |
7307 |
0 |
3 |
T23 |
1784 |
1612 |
0 |
3 |
T24 |
28501 |
28229 |
0 |
3 |
T25 |
1388 |
1231 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
32542 |
0 |
0 |
T1 |
435017 |
83 |
0 |
0 |
T2 |
145997 |
1 |
0 |
0 |
T5 |
68911 |
1 |
0 |
0 |
T6 |
2522 |
16 |
0 |
0 |
T7 |
4113 |
17 |
0 |
0 |
T21 |
2356 |
4 |
0 |
0 |
T22 |
7537 |
27 |
0 |
0 |
T23 |
1784 |
3 |
0 |
0 |
T24 |
28501 |
10 |
0 |
0 |
T25 |
1388 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526461095 |
0 |
2415 |
T1 |
435017 |
433824 |
0 |
3 |
T2 |
145997 |
145911 |
0 |
3 |
T5 |
68911 |
68725 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
4113 |
3984 |
0 |
3 |
T21 |
2356 |
2141 |
0 |
3 |
T22 |
7537 |
7307 |
0 |
3 |
T23 |
1784 |
1612 |
0 |
3 |
T24 |
28501 |
28229 |
0 |
3 |
T25 |
1388 |
1231 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
32452 |
0 |
0 |
T1 |
435017 |
79 |
0 |
0 |
T2 |
145997 |
1 |
0 |
0 |
T5 |
68911 |
1 |
0 |
0 |
T6 |
2522 |
22 |
0 |
0 |
T7 |
4113 |
21 |
0 |
0 |
T21 |
2356 |
4 |
0 |
0 |
T22 |
7537 |
11 |
0 |
0 |
T23 |
1784 |
3 |
0 |
0 |
T24 |
28501 |
10 |
0 |
0 |
T25 |
1388 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526461095 |
0 |
2415 |
T1 |
435017 |
433824 |
0 |
3 |
T2 |
145997 |
145911 |
0 |
3 |
T5 |
68911 |
68725 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
4113 |
3984 |
0 |
3 |
T21 |
2356 |
2141 |
0 |
3 |
T22 |
7537 |
7307 |
0 |
3 |
T23 |
1784 |
1612 |
0 |
3 |
T24 |
28501 |
28229 |
0 |
3 |
T25 |
1388 |
1231 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
32792 |
0 |
0 |
T1 |
435017 |
72 |
0 |
0 |
T2 |
145997 |
1 |
0 |
0 |
T5 |
68911 |
1 |
0 |
0 |
T6 |
2522 |
22 |
0 |
0 |
T7 |
4113 |
8 |
0 |
0 |
T21 |
2356 |
4 |
0 |
0 |
T22 |
7537 |
15 |
0 |
0 |
T23 |
1784 |
3 |
0 |
0 |
T24 |
28501 |
13 |
0 |
0 |
T25 |
1388 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526461095 |
0 |
2415 |
T1 |
435017 |
433824 |
0 |
3 |
T2 |
145997 |
145911 |
0 |
3 |
T5 |
68911 |
68725 |
0 |
3 |
T6 |
2522 |
2265 |
0 |
3 |
T7 |
4113 |
3984 |
0 |
3 |
T21 |
2356 |
2141 |
0 |
3 |
T22 |
7537 |
7307 |
0 |
3 |
T23 |
1784 |
1612 |
0 |
3 |
T24 |
28501 |
28229 |
0 |
3 |
T25 |
1388 |
1231 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
32431 |
0 |
0 |
T1 |
435017 |
77 |
0 |
0 |
T2 |
145997 |
1 |
0 |
0 |
T5 |
68911 |
1 |
0 |
0 |
T6 |
2522 |
20 |
0 |
0 |
T7 |
4113 |
21 |
0 |
0 |
T21 |
2356 |
4 |
0 |
0 |
T22 |
7537 |
27 |
0 |
0 |
T23 |
1784 |
3 |
0 |
0 |
T24 |
28501 |
13 |
0 |
0 |
T25 |
1388 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530518557 |
526467750 |
0 |
0 |
T1 |
435017 |
433848 |
0 |
0 |
T2 |
145997 |
145914 |
0 |
0 |
T5 |
68911 |
68728 |
0 |
0 |
T6 |
2522 |
2268 |
0 |
0 |
T7 |
4113 |
3987 |
0 |
0 |
T21 |
2356 |
2144 |
0 |
0 |
T22 |
7537 |
7310 |
0 |
0 |
T23 |
1784 |
1615 |
0 |
0 |
T24 |
28501 |
28232 |
0 |
0 |
T25 |
1388 |
1234 |
0 |
0 |