Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	158545477	156091667	0	0
AllClkBypReqTrue_A	158545477	123571	0	0
IoClkBypReqFalse_A	158545477	156013380	0	2415
IoClkBypReqTrue_A	158545477	197450	0	0
LcClkBypAckFalse_A	158545477	156099733	0	0
LcClkBypAckTrue_A	158545477	115505	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	156091667	0	0
T1	440642	439515	0	0
T2	35038	35018	0	0
T5	17978	17933	0	0
T6	2522	2026	0	0
T7	1726	1488	0	0
T21	2285	2079	0	0
T22	1883	1683	0	0
T23	1748	1582	0	0
T24	1709	1652	0	0
T25	1452	1297	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	123571	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	0	3070	0	0
T6	2522	241	0	0
T7	1726	185	0	0
T15	2256	0	0	0
T18	0	42	0	0
T20	0	37	0	0
T21	2285	0	0	0
T22	1883	143	0	0
T23	1748	0	0	0
T24	1709	40	0	0
T25	1452	0	0	0
T73	0	18	0	0
T86	0	202	0	0
T107	0	61	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	156013380	0	2415
T1	440642	439499	0	3
T2	35038	35016	0	3
T5	17978	17931	0	3
T6	2522	1958	0	3
T7	1726	1624	0	3
T21	2285	2077	0	3
T22	1883	1429	0	3
T23	1748	1580	0	3
T24	1709	1378	0	3
T25	1452	1295	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	197450	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	0	4016	0	0
T6	2522	307	0	0
T7	1726	47	0	0
T12	0	1978	0	0
T15	2256	0	0	0
T18	0	153	0	0
T21	2285	0	0	0
T22	1883	395	0	0
T23	1748	0	0	0
T24	1709	312	0	0
T25	1452	0	0	0
T72	0	33	0	0
T86	0	323	0	0
T108	0	42	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	156099733	0	0
T1	440642	439515	0	0
T2	35038	35018	0	0
T5	17978	17933	0	0
T6	2522	2105	0	0
T7	1726	1629	0	0
T21	2285	2079	0	0
T22	1883	1645	0	0
T23	1748	1582	0	0
T24	1709	1571	0	0
T25	1452	1297	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	115505	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	0	2231	0	0
T6	2522	162	0	0
T7	1726	44	0	0
T12	0	1229	0	0
T13	0	1841	0	0
T15	2256	0	0	0
T18	0	53	0	0
T21	2285	0	0	0
T22	1883	181	0	0
T23	1748	0	0	0
T24	1709	121	0	0
T25	1452	0	0	0
T72	0	29	0	0
T86	0	165	0	0