Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2122076060	15984	0	0
TransStop_A	2122076060	8169	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122076060	15984	0	0
T1	1740072	76	0	0
T2	583992	0	0	0
T3	0	201	0	0
T10	0	74	0	0
T12	0	78	0	0
T13	0	589	0	0
T14	0	211	0	0
T15	36104	39	0	0
T16	16216	0	0	0
T17	6488	0	0	0
T19	0	29	0	0
T21	9424	4	0	0
T22	30152	0	0	0
T23	7136	0	0	0
T24	114004	0	0	0
T25	5556	0	0	0
T74	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122076060	8169	0	0
T1	1740072	46	0	0
T2	583992	0	0	0
T3	0	109	0	0
T10	0	33	0	0
T12	0	42	0	0
T13	0	262	0	0
T14	0	116	0	0
T15	36104	16	0	0
T16	16216	0	0	0
T17	6488	0	0	0
T19	0	19	0	0
T21	9424	4	0	0
T22	30152	0	0	0
T23	7136	0	0	0
T24	114004	0	0	0
T25	5556	0	0	0
T74	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	530519015	3973	0	0
TransStop_A	530519015	2044	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	3973	0	0
T1	435018	24	0	0
T2	145998	0	0	0
T3	0	47	0	0
T10	0	17	0	0
T12	0	19	0	0
T13	0	139	0	0
T14	0	51	0	0
T15	9026	13	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	2044	0	0
T1	435018	15	0	0
T2	145998	0	0	0
T3	0	26	0	0
T10	0	9	0	0
T12	0	10	0	0
T13	0	63	0	0
T14	0	30	0	0
T15	9026	6	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	2	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	530519015	4052	0	0
TransStop_A	530519015	2073	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	4052	0	0
T1	435018	17	0	0
T2	145998	0	0	0
T3	0	50	0	0
T10	0	24	0	0
T12	0	19	0	0
T13	0	148	0	0
T14	0	52	0	0
T15	9026	9	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	12	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	2073	0	0
T1	435018	9	0	0
T2	145998	0	0	0
T3	0	27	0	0
T10	0	12	0	0
T12	0	11	0	0
T13	0	68	0	0
T14	0	28	0	0
T15	9026	4	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	8	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	530519015	4011	0	0
TransStop_A	530519015	2028	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	4011	0	0
T1	435018	18	0	0
T2	145998	0	0	0
T3	0	49	0	0
T10	0	20	0	0
T12	0	19	0	0
T13	0	151	0	0
T14	0	48	0	0
T15	9026	9	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	2028	0	0
T1	435018	11	0	0
T2	145998	0	0	0
T3	0	27	0	0
T10	0	7	0	0
T12	0	10	0	0
T13	0	60	0	0
T14	0	27	0	0
T15	9026	3	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	2	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	530519015	3948	0	0
TransStop_A	530519015	2024	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	3948	0	0
T1	435018	17	0	0
T2	145998	0	0	0
T3	0	55	0	0
T10	0	13	0	0
T12	0	21	0	0
T13	0	151	0	0
T14	0	60	0	0
T15	9026	8	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	9	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530519015	2024	0	0
T1	435018	11	0	0
T2	145998	0	0	0
T3	0	29	0	0
T10	0	5	0	0
T12	0	11	0	0
T13	0	71	0	0
T14	0	31	0	0
T15	9026	3	0	0
T16	4054	0	0	0
T17	1622	0	0	0
T19	0	7	0	0
T21	2356	1	0	0
T22	7538	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1389	0	0	0
T74	0	1	0	0