Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
46 |
46 |
100.00 |
Total Bits 0->1 |
23 |
23 |
100.00 |
Total Bits 1->0 |
23 |
23 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
46 |
46 |
100.00 |
Port Bits 0->1 |
23 |
23 |
100.00 |
Port Bits 1->0 |
23 |
23 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
oh_i[2:0] |
Yes |
Yes |
*T23,*T31,*T32 |
Yes |
T23,T31,T32 |
INPUT |
oh_i[3] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[7:4] |
Yes |
Yes |
*T47,*T36,*T37 |
Yes |
T47,T36,T37 |
INPUT |
oh_i[8] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[20:9] |
Yes |
Yes |
T5,T1,T2 |
Yes |
T5,T1,T2 |
INPUT |
oh_i[21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
err_o |
Yes |
Yes |
T47,T36,T48 |
Yes |
T47,T36,T48 |
OUTPUT |
*Tests covering at least one bit in the range