Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	158545477	19225408	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	19225408	0	59
T1	440642	12585	0	0
T2	35038	9728	0	1
T3	324792	118290	0	0
T4	25635	0	0	0
T8	0	3762	0	1
T9	0	25212	0	1
T10	0	12708	0	0
T11	0	47360	0	1
T12	0	433257	0	0
T13	0	199717	0	0
T14	0	147111	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0
T26	0	0	0	1
T42	0	0	0	1
T76	0	0	0	1
T109	0	0	0	1
T110	0	0	0	1
T111	0	0	0	1