Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	159359069	5494719	0	0
clk_enables_rd_A	159359069	34009	0	0
clk_hints_rd_A	159359069	31443	0	0
extclk_ctrl_rd_A	159359069	39740	0	0
extclk_ctrl_regwen_rd_A	159359069	29408	0	0
jitter_enable_rd_A	159359069	46874	0	0
jitter_regwen_rd_A	159359069	33553	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	5494719	0	0
T3	324792	90371	0	0
T8	11573	0	0	0
T9	152190	0	0	0
T12	0	68243	0	0
T13	0	166085	0	0
T14	0	136037	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0
T27	0	88574	0	0
T28	46153	0	0	0
T29	0	164821	0	0
T68	0	80752	0	0
T69	0	87572	0	0
T70	0	221850	0	0
T71	0	214230	0	0
T72	1156	0	0	0
T73	907	0	0	0
T74	1347	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	34009	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	0	3203	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T21	2285	3	0	0
T22	1883	0	0	0
T23	1748	0	0	0
T24	1709	0	0	0
T25	1452	0	0	0
T39	0	4	0	0
T68	0	2956	0	0
T131	0	16	0	0
T132	0	4	0	0
T133	0	2210	0	0
T134	0	2760	0	0
T135	0	2	0	0
T136	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	31443	0	0
T3	324792	2860	0	0
T8	11573	0	0	0
T9	152190	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0
T28	46153	0	0	0
T68	0	2562	0	0
T72	1156	0	0	0
T73	907	0	0	0
T74	1347	0	0	0
T131	0	7	0	0
T132	0	8	0	0
T133	0	1969	0	0
T134	0	2426	0	0
T135	0	1	0	0
T137	0	6	0	0
T138	0	3	0	0
T139	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	39740	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	3948	0	0
T4	25635	109	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T18	1004	5	0	0
T24	1709	36	0	0
T25	1452	0	0	0
T68	0	3271	0	0
T88	0	60	0	0
T140	0	19	0	0
T141	0	13	0	0
T142	0	7	0	0
T143	0	60	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	29408	0	0
T3	324792	2733	0	0
T4	25635	42	0	0
T8	11573	0	0	0
T9	152190	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0
T28	46153	0	0	0
T40	0	11	0	0
T68	0	2729	0	0
T72	1156	0	0	0
T73	907	0	0	0
T105	0	75	0	0
T133	0	1990	0	0
T134	0	2484	0	0
T141	0	8	0	0
T144	0	21	0	0
T145	0	23	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	46874	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	0	3943	0	0
T15	2256	0	0	0
T16	1074	0	0	0
T17	1634	0	0	0
T21	2285	83	0	0
T22	1883	0	0	0
T23	1748	0	0	0
T24	1709	0	0	0
T25	1452	0	0	0
T39	0	55	0	0
T68	0	4017	0	0
T131	0	365	0	0
T132	0	72	0	0
T133	0	3266	0	0
T134	0	3663	0	0
T137	0	81	0	0
T146	0	59	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159359069	33553	0	0
T3	324792	3460	0	0
T8	11573	0	0	0
T9	152190	0	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T20	1541	0	0	0
T28	46153	0	0	0
T68	0	3383	0	0
T72	1156	0	0	0
T73	907	0	0	0
T74	1347	0	0	0
T133	0	2396	0	0
T134	0	2975	0	0
T147	0	2452	0	0
T148	0	2837	0	0
T149	0	1007	0	0
T150	0	1537	0	0
T151	0	1384	0	0
T152	0	3142	0	0