Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	475636431	481	0	0
StatusRise_A	475636431	481	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475636431	481	0	0
T1	1321926	0	0	0
T2	105114	0	0	0
T3	974376	0	0	0
T4	76905	0	0	0
T15	6768	0	0	0
T16	3222	9	0	0
T17	4902	6	0	0
T18	3012	0	0	0
T19	8667	0	0	0
T25	4356	7	0	0
T51	0	6	0	0
T53	0	15	0	0
T153	0	11	0	0
T154	0	16	0	0
T155	0	5	0	0
T156	0	14	0	0
T157	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475636431	481	0	0
T1	1321926	0	0	0
T2	105114	0	0	0
T3	974376	0	0	0
T4	76905	0	0	0
T15	6768	0	0	0
T16	3222	9	0	0
T17	4902	6	0	0
T18	3012	0	0	0
T19	8667	0	0	0
T25	4356	7	0	0
T51	0	6	0	0
T53	0	15	0	0
T153	0	11	0	0
T154	0	16	0	0
T155	0	5	0	0
T156	0	14	0	0
T157	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158545477	158	0	0
StatusRise_A	158545477	158	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	158	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	3	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	6	0	0
T157	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	158	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	3	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	6	0	0
T157	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158545477	156	0	0
StatusRise_A	158545477	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	156	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	4	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	156	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	4	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	158545477	167	0	0
StatusRise_A	158545477	167	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	167	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	2	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	6	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158545477	167	0	0
T1	440642	0	0	0
T2	35038	0	0	0
T3	324792	0	0	0
T4	25635	0	0	0
T15	2256	0	0	0
T16	1074	2	0	0
T17	1634	2	0	0
T18	1004	0	0	0
T19	2889	0	0	0
T25	1452	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	6	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0