Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47611	0	0
CgEnOn_A	2147483647	38789	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47611	0	0
T1	4576238	56	0	0
T2	1576650	3	0	0
T3	3233554	47	0	0
T4	570214	0	0	0
T5	118557	3	0	0
T6	5578	3	0	0
T7	9134	3	0	0
T13	0	5	0	0
T15	77883	13	0	0
T16	34603	23	0	0
T17	13893	12	0	0
T18	79279	0	0	0
T19	55727	0	0	0
T21	14441	7	0	0
T22	46998	3	0	0
T23	10959	3	0	0
T24	177136	3	0	0
T25	14768	29	0	0
T51	0	10	0	0
T53	0	25	0	0
T153	0	15	0	0
T154	0	35	0	0
T155	0	10	0	0
T156	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38789	0	0
T1	4576238	49	0	0
T2	1576650	0	0	0
T3	3233554	317	0	0
T4	570214	0	0	0
T10	0	44	0	0
T12	0	116	0	0
T13	0	4	0	0
T15	97318	22	0	0
T16	43040	41	0	0
T17	17340	22	0	0
T18	79279	0	0	0
T19	55727	16	0	0
T21	14441	5	0	0
T22	46998	0	0	0
T23	10959	0	0	0
T24	177136	0	0	0
T25	14768	30	0	0
T51	0	12	0	0
T53	0	30	0	0
T74	0	5	0	0
T133	0	1	0	0
T153	0	20	0	0
T154	0	38	0	0
T155	0	12	0	0
T156	0	21	0	0
T157	0	4	0	0
T158	0	19	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	248772914	163	0	0
CgEnOn_A	248772914	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248772914	163	0	0
T1	191286	0	0	0
T2	70051	0	0	0
T3	134538	0	0	0
T4	42430	0	0	0
T13	0	1	0	0
T15	4293	0	0	0
T16	1848	4	0	0
T17	720	2	0	0
T18	8672	0	0	0
T19	5720	0	0	0
T25	635	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248772914	163	0	0
T1	191286	0	0	0
T2	70051	0	0	0
T3	134538	0	0	0
T4	42430	0	0	0
T13	0	1	0	0
T15	4293	0	0	0
T16	1848	4	0	0
T17	720	2	0	0
T18	8672	0	0	0
T19	5720	0	0	0
T25	635	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124385862	163	0	0
CgEnOn_A	124385862	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124385862	163	0	0
CgEnOn_A	124385862	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124385862	163	0	0
CgEnOn_A	124385862	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	163	0	0
T1	95643	0	0	0
T2	35025	0	0	0
T3	672681	0	0	0
T4	21214	0	0	0
T13	0	1	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T18	4336	0	0	0
T19	2860	0	0	0
T25	317	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	497177267	163	0	0
CgEnOn_A	497177267	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177267	163	0	0
T1	383044	0	0	0
T2	140153	0	0	0
T3	270074	0	0	0
T4	129525	0	0	0
T13	0	1	0	0
T15	8664	0	0	0
T16	3733	4	0	0
T17	1574	2	0	0
T18	16074	0	0	0
T19	11561	0	0	0
T25	1335	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177267	157	0	0
T1	383044	0	0	0
T2	140153	0	0	0
T3	270074	0	0	0
T4	129525	0	0	0
T15	8664	0	0	0
T16	3733	4	0	0
T17	1574	2	0	0
T18	16074	0	0	0
T19	11561	0	0	0
T25	1335	3	0	0
T51	0	2	0	0
T53	0	5	0	0
T133	0	1	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	160	0	0
CgEnOn_A	530518557	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	160	0	0
T1	435017	0	0	0
T2	145997	0	0	0
T3	328136	0	0	0
T4	134926	0	0	0
T14	0	1	0	0
T15	9026	0	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T18	16744	0	0	0
T19	12043	0	0	0
T25	1388	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T69	0	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	158	0	0
T1	435017	0	0	0
T2	145997	0	0	0
T3	328136	0	0	0
T4	134926	0	0	0
T15	9026	0	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T18	16744	0	0	0
T19	12043	0	0	0
T25	1388	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	6	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	160	0	0
CgEnOn_A	530518557	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	160	0	0
T1	435017	0	0	0
T2	145997	0	0	0
T3	328136	0	0	0
T4	134926	0	0	0
T14	0	1	0	0
T15	9026	0	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T18	16744	0	0	0
T19	12043	0	0	0
T25	1388	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T69	0	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	158	0	0
T1	435017	0	0	0
T2	145997	0	0	0
T3	328136	0	0	0
T4	134926	0	0	0
T15	9026	0	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T18	16744	0	0	0
T19	12043	0	0	0
T25	1388	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	6	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	254702600	170	0	0
CgEnOn_A	254702600	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254702600	170	0	0
T1	217452	0	0	0
T2	70080	0	0	0
T3	154627	0	0	0
T4	64765	0	0	0
T13	0	1	0	0
T15	4332	0	0	0
T16	1932	2	0	0
T17	793	2	0	0
T18	8037	0	0	0
T19	5780	0	0	0
T25	616	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	6	0	0
T155	0	1	0	0
T156	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254702600	167	0	0
T1	217452	0	0	0
T2	70080	0	0	0
T3	154627	0	0	0
T4	64765	0	0	0
T15	4332	0	0	0
T16	1932	2	0	0
T17	793	2	0	0
T18	8037	0	0	0
T19	5780	0	0	0
T25	616	2	0	0
T51	0	2	0	0
T53	0	5	0	0
T153	0	3	0	0
T154	0	6	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T16,T17
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124385862	7394	0	0
CgEnOn_A	124385862	5197	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	7394	0	0
T1	95643	9	0	0
T2	35025	1	0	0
T5	12202	1	0	0
T6	648	1	0	0
T7	1070	1	0	0
T21	542	2	0	0
T22	1998	1	0	0
T23	418	1	0	0
T24	7363	1	0	0
T25	317	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124385862	5197	0	0
T1	95643	1	0	0
T2	35025	0	0	0
T3	0	75	0	0
T10	0	1	0	0
T12	0	41	0	0
T15	2146	0	0	0
T16	924	4	0	0
T17	360	2	0	0
T21	542	1	0	0
T22	1998	0	0	0
T23	418	0	0	0
T24	7363	0	0	0
T25	317	3	0	0
T74	0	1	0	0
T158	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T16,T17
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	248772914	7447	0	0
CgEnOn_A	248772914	5250	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248772914	7447	0	0
T1	191286	11	0	0
T2	70051	1	0	0
T5	24404	1	0	0
T6	1298	1	0	0
T7	2142	1	0	0
T21	1084	2	0	0
T22	4000	1	0	0
T23	837	1	0	0
T24	14729	1	0	0
T25	635	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248772914	5250	0	0
T1	191286	3	0	0
T2	70051	0	0	0
T3	0	74	0	0
T10	0	1	0	0
T12	0	36	0	0
T15	4293	0	0	0
T16	1848	4	0	0
T17	720	2	0	0
T21	1084	1	0	0
T22	4000	0	0	0
T23	837	0	0	0
T24	14729	0	0	0
T25	635	3	0	0
T74	0	1	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T16,T17
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	497177267	7411	0	0
CgEnOn_A	497177267	5208	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177267	7411	0	0
T1	383044	12	0	0
T2	140153	1	0	0
T5	48873	1	0	0
T6	2422	1	0	0
T7	3948	1	0	0
T21	2261	2	0	0
T22	7235	1	0	0
T23	1712	1	0	0
T24	27360	1	0	0
T25	1335	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497177267	5208	0	0
T1	383044	4	0	0
T2	140153	0	0	0
T3	0	71	0	0
T10	0	1	0	0
T12	0	39	0	0
T15	8664	0	0	0
T16	3733	4	0	0
T17	1574	2	0	0
T21	2261	1	0	0
T22	7235	0	0	0
T23	1712	0	0	0
T24	27360	0	0	0
T25	1335	3	0	0
T74	0	1	0	0
T158	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T16,T17
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	254702600	7430	0	0
CgEnOn_A	254702600	5226	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254702600	7430	0	0
T1	217452	9	0	0
T2	70080	1	0	0
T5	33078	1	0	0
T6	1210	1	0	0
T7	1974	1	0	0
T21	1130	2	0	0
T22	3617	1	0	0
T23	856	1	0	0
T24	13680	1	0	0
T25	616	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254702600	5226	0	0
T1	217452	1	0	0
T2	70080	0	0	0
T3	0	71	0	0
T10	0	1	0	0
T12	0	40	0	0
T15	4332	0	0	0
T16	1932	2	0	0
T17	793	2	0	0
T21	1130	1	0	0
T22	3617	0	0	0
T23	856	0	0	0
T24	13680	0	0	0
T25	616	2	0	0
T74	0	1	0	0
T158	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Covered	T21,T1,T15
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	4133	0	0
CgEnOn_A	530518557	4131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4133	0	0
T1	435017	24	0	0
T2	145997	0	0	0
T3	0	47	0	0
T10	0	17	0	0
T15	9026	13	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4131	0	0
T1	435017	24	0	0
T2	145997	0	0	0
T3	0	47	0	0
T10	0	17	0	0
T15	9026	13	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Covered	T21,T1,T15
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	4212	0	0
CgEnOn_A	530518557	4210	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4212	0	0
T1	435017	17	0	0
T2	145997	0	0	0
T3	0	50	0	0
T10	0	24	0	0
T15	9026	9	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	12	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4210	0	0
T1	435017	17	0	0
T2	145997	0	0	0
T3	0	50	0	0
T10	0	24	0	0
T15	9026	9	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	12	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Covered	T21,T1,T15
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	4171	0	0
CgEnOn_A	530518557	4169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4171	0	0
T1	435017	18	0	0
T2	145997	0	0	0
T3	0	49	0	0
T10	0	20	0	0
T15	9026	9	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4169	0	0
T1	435017	18	0	0
T2	145997	0	0	0
T3	0	49	0	0
T10	0	20	0	0
T15	9026	9	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	4	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T1,T16
1	0	Covered	T21,T1,T15
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	530518557	4108	0	0
CgEnOn_A	530518557	4106	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4108	0	0
T1	435017	17	0	0
T2	145997	0	0	0
T3	0	55	0	0
T10	0	13	0	0
T15	9026	8	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	9	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530518557	4106	0	0
T1	435017	17	0	0
T2	145997	0	0	0
T3	0	55	0	0
T10	0	13	0	0
T15	9026	8	0	0
T16	4053	3	0	0
T17	1621	2	0	0
T19	0	9	0	0
T21	2356	1	0	0
T22	7537	0	0	0
T23	1784	0	0	0
T24	28501	0	0	0
T25	1388	2	0	0
T74	0	1	0	0