Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	658370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3921435

1

T5

15

T6

11

T7

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1120724	1			T5	10		T6	13		T7	36
values[0x0]	1591321	1			T5	11		T6	12		T7	12
values[0x1]	1867760	1			T5	10		T6	15		T7	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	359932	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4219873

1

T5

19

T6

12

T7

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15600	1			T5	1		T27	3		T1	2
valid_sources[0x01]	17732	1			T27	1		T1	2		T2	314
valid_sources[0x02]	17508	1			T1	2		T2	278		T3	22
valid_sources[0x03]	18908	1			T1	2		T2	262		T3	50
valid_sources[0x04]	20861	1			T2	283		T3	35		T9	288
valid_sources[0x05]	16959	1			T27	1		T2	282		T3	196
valid_sources[0x06]	17813	1			T1	3		T2	243		T3	17
valid_sources[0x07]	16994	1			T27	3		T1	3		T2	269
valid_sources[0x08]	17173	1			T7	1		T2	318		T3	263
valid_sources[0x09]	17790	1			T27	2		T1	1		T2	297
valid_sources[0x0a]	18314	1			T1	4		T2	302		T3	117
valid_sources[0x0b]	18330	1			T1	1		T2	257		T3	19
valid_sources[0x0c]	19036	1			T22	1		T1	6		T2	307
valid_sources[0x0d]	20529	1			T7	1		T22	4		T23	6
valid_sources[0x0e]	18290	1			T2	286		T3	115		T9	409
valid_sources[0x0f]	20130	1			T27	3		T1	2		T2	314
valid_sources[0x10]	16931	1			T22	3		T1	12		T2	304
valid_sources[0x11]	17365	1			T7	1		T1	1		T2	262
valid_sources[0x12]	17344	1			T7	2		T1	1		T2	277
valid_sources[0x13]	16370	1			T1	5		T2	306		T3	18
valid_sources[0x14]	17742	1			T7	1		T23	1		T2	286
valid_sources[0x15]	16850	1			T2	261		T3	127		T9	311
valid_sources[0x16]	16989	1			T1	4		T2	237		T3	11
valid_sources[0x17]	17219	1			T7	1		T1	1		T2	287
valid_sources[0x18]	17554	1			T22	1		T1	3		T2	329
valid_sources[0x19]	15341	1			T27	2		T2	286		T3	166
valid_sources[0x1a]	19378	1			T22	4		T1	3		T2	268
valid_sources[0x1b]	17451	1			T22	1		T27	7		T2	282
valid_sources[0x1c]	18605	1			T1	1		T2	323		T3	224
valid_sources[0x1d]	17128	1			T5	1		T1	4		T2	289
valid_sources[0x1e]	17645	1			T27	4		T2	273		T3	22
valid_sources[0x1f]	15675	1			T5	1		T1	4		T2	238
valid_sources[0x20]	19121	1			T7	1		T1	8		T2	255
valid_sources[0x21]	18460	1			T7	1		T27	1		T2	280
valid_sources[0x22]	18633	1			T1	3		T2	283		T3	314
valid_sources[0x23]	17560	1			T2	292		T3	238		T9	192
valid_sources[0x24]	17411	1			T27	1		T1	2		T2	278
valid_sources[0x25]	18234	1			T1	1		T2	268		T3	180
valid_sources[0x26]	18834	1			T7	1		T1	5		T2	323
valid_sources[0x27]	18346	1			T1	2		T2	279		T3	144
valid_sources[0x28]	17068	1			T7	1		T1	1		T2	292
valid_sources[0x29]	17416	1			T22	1		T2	266		T3	197
valid_sources[0x2a]	17023	1			T22	1		T1	1		T2	268
valid_sources[0x2b]	17468	1			T1	2		T2	285		T3	8
valid_sources[0x2c]	16948	1			T1	4		T2	267		T3	14
valid_sources[0x2d]	17467	1			T1	1		T2	273		T3	106
valid_sources[0x2e]	18393	1			T7	1		T1	7		T2	296
valid_sources[0x2f]	18859	1			T22	3		T2	275		T3	155
valid_sources[0x30]	16936	1			T1	4		T2	296		T3	22
valid_sources[0x31]	17815	1			T1	5		T2	290		T3	130
valid_sources[0x32]	18427	1			T1	1		T2	302		T3	8
valid_sources[0x33]	18138	1			T27	8		T2	284		T3	11
valid_sources[0x34]	18479	1			T7	1		T23	17		T24	2
valid_sources[0x35]	17494	1			T1	1		T2	269		T3	628
valid_sources[0x36]	18391	1			T1	4		T2	324		T3	16
valid_sources[0x37]	17042	1			T22	1		T1	5		T2	273
valid_sources[0x38]	15923	1			T7	1		T1	2		T2	307
valid_sources[0x39]	16578	1			T5	2		T22	1		T1	4
valid_sources[0x3a]	16430	1			T7	1		T1	2		T2	261
valid_sources[0x3b]	19302	1			T1	6		T2	277		T3	166
valid_sources[0x3c]	17077	1			T1	4		T2	253		T3	145
valid_sources[0x3d]	17803	1			T27	1		T1	1		T2	318
valid_sources[0x3e]	18125	1			T7	1		T22	2		T27	2
valid_sources[0x3f]	17693	1			T22	2		T1	8		T2	274
valid_sources[0x40]	18145	1			T27	4		T1	5		T2	278
valid_sources[0x41]	16984	1			T7	1		T2	270		T3	407
valid_sources[0x42]	18251	1			T1	2		T2	261		T3	4
valid_sources[0x43]	19145	1			T1	8		T2	293		T3	29
valid_sources[0x44]	16540	1			T7	2		T2	280		T3	108
valid_sources[0x45]	19135	1			T1	3		T2	318		T20	5
valid_sources[0x46]	17574	1			T22	3		T27	1		T1	5
valid_sources[0x47]	18898	1			T27	2		T1	4		T2	297
valid_sources[0x48]	19385	1			T1	4		T2	265		T3	151
valid_sources[0x49]	17663	1			T1	1		T2	253		T3	14
valid_sources[0x4a]	16630	1			T1	1		T2	278		T3	8
valid_sources[0x4b]	17629	1			T2	299		T3	222		T9	412
valid_sources[0x4c]	17872	1			T1	2		T2	309		T3	20
valid_sources[0x4d]	16534	1			T1	1		T2	272		T3	13
valid_sources[0x4e]	17897	1			T27	1		T1	1		T2	296
valid_sources[0x4f]	18182	1			T27	1		T1	6		T2	277
valid_sources[0x50]	18243	1			T1	5		T2	299		T3	11
valid_sources[0x51]	18773	1			T1	4		T2	279		T3	27
valid_sources[0x52]	17243	1			T6	40		T1	2		T2	265
valid_sources[0x53]	17393	1			T7	4		T27	1		T1	1
valid_sources[0x54]	17418	1			T1	6		T2	290		T3	236
valid_sources[0x55]	16843	1			T1	3		T2	291		T3	15
valid_sources[0x56]	18360	1			T1	3		T2	293		T3	122
valid_sources[0x57]	19398	1			T2	274		T3	383		T9	853
valid_sources[0x58]	19000	1			T7	1		T27	1		T2	259
valid_sources[0x59]	18126	1			T22	2		T23	2		T24	1
valid_sources[0x5a]	18691	1			T5	1		T24	2		T27	3
valid_sources[0x5b]	17339	1			T23	1		T1	4		T2	313
valid_sources[0x5c]	17799	1			T5	1		T1	3		T2	294
valid_sources[0x5d]	17958	1			T24	1		T1	1		T16	81
valid_sources[0x5e]	17942	1			T1	5		T2	279		T3	15
valid_sources[0x5f]	16795	1			T5	1		T1	1		T2	288
valid_sources[0x60]	17778	1			T27	1		T2	280		T3	78
valid_sources[0x61]	19538	1			T1	5		T2	268		T3	245
valid_sources[0x62]	18388	1			T7	2		T22	1		T1	4
valid_sources[0x63]	17833	1			T27	1		T1	5		T2	294
valid_sources[0x64]	18621	1			T5	3		T1	1		T2	300
valid_sources[0x65]	17281	1			T7	1		T1	2		T2	294
valid_sources[0x66]	19489	1			T7	1		T1	8		T2	269
valid_sources[0x67]	18450	1			T2	287		T3	8		T9	327
valid_sources[0x68]	15855	1			T7	1		T1	1		T2	293
valid_sources[0x69]	17124	1			T7	1		T22	4		T24	1
valid_sources[0x6a]	17094	1			T1	3		T2	294		T3	183
valid_sources[0x6b]	17363	1			T1	2		T2	279		T3	20
valid_sources[0x6c]	17832	1			T1	2		T2	264		T3	20
valid_sources[0x6d]	17487	1			T22	4		T2	254		T3	44
valid_sources[0x6e]	18167	1			T27	3		T2	263		T3	450
valid_sources[0x6f]	18333	1			T5	2		T1	2		T2	275
valid_sources[0x70]	17955	1			T22	4		T2	274		T3	8
valid_sources[0x71]	19983	1			T1	1		T2	298		T3	4
valid_sources[0x72]	17754	1			T22	1		T25	105		T2	271
valid_sources[0x73]	18216	1			T5	1		T1	4		T2	290
valid_sources[0x74]	17743	1			T1	1		T2	296		T3	98
valid_sources[0x75]	17832	1			T2	259		T3	260		T9	853
valid_sources[0x76]	17477	1			T24	1		T1	1		T2	322
valid_sources[0x77]	16915	1			T1	5		T2	265		T3	2
valid_sources[0x78]	17610	1			T7	1		T2	267		T3	176
valid_sources[0x79]	16736	1			T1	2		T2	301		T3	24
valid_sources[0x7a]	19500	1			T1	1		T2	264		T3	55
valid_sources[0x7b]	16744	1			T27	1		T2	273		T3	7
valid_sources[0x7c]	18731	1			T27	3		T1	1		T2	297
valid_sources[0x7d]	18452	1			T1	2		T2	324		T3	244
valid_sources[0x7e]	19330	1			T1	2		T2	278		T3	122
valid_sources[0x7f]	18771	1			T7	1		T27	5		T2	273
valid_sources[0x80]	16464	1			T7	1		T22	6		T1	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

987284

1

T5

8

T6

5

T7

21

values[0x0]

all_enables

biggest_size

1492020

1

T5

5

T6

3

T7

3

values[0x1]

all_enables

biggest_size

1442131

1

T5

2

T6

3

T7

5