Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T4,T1
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T4,T1
1	0	Covered	T19,T42,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	952077967	13510	0	0
GateOpen_A	952077967	19898	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952077967	13510	0	0
T1	446136	0	0	0
T2	0	281	0	0
T3	0	89	0	0
T4	257084	0	0	0
T9	0	296	0	0
T10	0	268	0	0
T16	3395	2	0	0
T19	0	9	0	0
T22	4526	4	0	0
T23	25356	0	0	0
T24	3142	0	0	0
T25	70126	0	0	0
T26	7165	0	0	0
T27	7901	0	0	0
T31	0	45	0	0
T35	2937	0	0	0
T131	0	4	0	0
T148	0	36	0	0
T149	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952077967	19898	0	0
T1	0	8	0	0
T4	257084	80	0	0
T5	21894	4	0	0
T6	4595	4	0	0
T7	6073	0	0	0
T22	4526	8	0	0
T23	25356	4	0	0
T24	3142	4	0	0
T25	70126	4	0	0
T26	7165	0	0	0
T27	7901	4	0	0
T35	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T4,T1
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T4,T1
1	0	Covered	T19,T42,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104949226	3199	0	0
GateOpen_A	104949226	4795	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104949226	3199	0	0
T1	49970	0	0	0
T2	0	63	0	0
T3	0	21	0	0
T4	18962	0	0	0
T9	0	73	0	0
T10	0	61	0	0
T16	369	0	0	0
T19	0	2	0	0
T22	490	1	0	0
T23	3108	0	0	0
T24	339	0	0	0
T25	7776	0	0	0
T26	783	0	0	0
T27	856	0	0	0
T31	0	10	0	0
T35	304	0	0	0
T131	0	1	0	0
T148	0	8	0	0
T149	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104949226	4795	0	0
T1	0	2	0	0
T4	18962	20	0	0
T5	2602	1	0	0
T6	527	1	0	0
T7	664	0	0	0
T22	490	2	0	0
T23	3108	1	0	0
T24	339	1	0	0
T25	7776	1	0	0
T26	783	0	0	0
T27	856	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T4,T1
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T4,T1
1	0	Covered	T19,T42,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	209899238	3449	0	0
GateOpen_A	209899238	5045	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209899238	3449	0	0
T1	99946	0	0	0
T2	0	71	0	0
T3	0	23	0	0
T4	37924	0	0	0
T9	0	73	0	0
T10	0	69	0	0
T16	737	0	0	0
T19	0	2	0	0
T22	979	1	0	0
T23	6215	0	0	0
T24	679	0	0	0
T25	15552	0	0	0
T26	1566	0	0	0
T27	1711	0	0	0
T31	0	10	0	0
T35	608	0	0	0
T131	0	1	0	0
T148	0	9	0	0
T149	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209899238	5045	0	0
T1	0	2	0	0
T4	37924	20	0	0
T5	5207	1	0	0
T6	1057	1	0	0
T7	1328	0	0	0
T22	979	2	0	0
T23	6215	1	0	0
T24	679	1	0	0
T25	15552	1	0	0
T26	1566	0	0	0
T27	1711	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T4,T1
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T4,T1
1	0	Covered	T19,T42,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	420877385	3451	0	0
GateOpen_A	420877385	5049	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420877385	3451	0	0
T1	197477	0	0	0
T2	0	75	0	0
T3	0	23	0	0
T4	133463	0	0	0
T9	0	75	0	0
T10	0	70	0	0
T16	1526	1	0	0
T19	0	2	0	0
T22	2038	1	0	0
T23	10688	0	0	0
T24	1416	0	0	0
T25	31198	0	0	0
T26	3211	0	0	0
T27	3556	0	0	0
T31	0	13	0	0
T35	1350	0	0	0
T131	0	1	0	0
T148	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420877385	5049	0	0
T1	0	2	0	0
T4	133463	20	0	0
T5	9390	1	0	0
T6	2007	1	0	0
T7	2721	0	0	0
T22	2038	2	0	0
T23	10688	1	0	0
T24	1416	1	0	0
T25	31198	1	0	0
T26	3211	0	0	0
T27	3556	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T4,T1
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T4,T1
1	0	Covered	T19,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	216352118	3411	0	0
GateOpen_A	216352118	5009	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216352118	3411	0	0
T1	98743	0	0	0
T2	0	72	0	0
T3	0	22	0	0
T4	66735	0	0	0
T9	0	75	0	0
T10	0	68	0	0
T16	763	1	0	0
T19	0	3	0	0
T22	1019	1	0	0
T23	5345	0	0	0
T24	708	0	0	0
T25	15600	0	0	0
T26	1605	0	0	0
T27	1778	0	0	0
T31	0	12	0	0
T35	675	0	0	0
T131	0	1	0	0
T148	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216352118	5009	0	0
T1	0	2	0	0
T4	66735	20	0	0
T5	4695	1	0	0
T6	1004	1	0	0
T7	1360	0	0	0
T22	1019	2	0	0
T23	5345	1	0	0
T24	708	1	0	0
T25	15600	1	0	0
T26	1605	0	0	0
T27	1778	1	0	0
T35	0	1	0	0