Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	832994660	76526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832994660	76526	0	0
T1	226275	82	0	0
T2	1359430	562	0	0
T3	541135	324	0	0
T9	2588915	2627	0	0
T10	0	2250	0	0
T11	0	113	0	0
T12	0	1451	0	0
T13	0	421	0	0
T14	0	96	0	0
T15	0	804	0	0
T16	7625	0	0	0
T17	13480	0	0	0
T18	7235	0	0	0
T19	6415	0	0	0
T20	3285	0	0	0
T21	7460	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166598932	11119	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	11119	0	0
T1	45255	13	0	0
T2	271886	90	0	0
T3	108227	61	0	0
T9	517783	345	0	0
T10	0	326	0	0
T11	0	14	0	0
T12	0	247	0	0
T13	0	54	0	0
T14	0	19	0	0
T15	0	105	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T18	1447	0	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166598932	11013	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	11013	0	0
T1	45255	13	0	0
T2	271886	88	0	0
T3	108227	61	0	0
T9	517783	337	0	0
T10	0	321	0	0
T11	0	14	0	0
T12	0	247	0	0
T13	0	61	0	0
T14	0	19	0	0
T15	0	103	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T18	1447	0	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166598932	15535	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	15535	0	0
T1	45255	17	0	0
T2	271886	110	0	0
T3	108227	62	0	0
T9	517783	541	0	0
T10	0	446	0	0
T11	0	23	0	0
T12	0	291	0	0
T13	0	84	0	0
T14	0	19	0	0
T15	0	162	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T18	1447	0	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166598932	15370	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	15370	0	0
T1	45255	16	0	0
T2	271886	115	0	0
T3	108227	62	0	0
T9	517783	531	0	0
T10	0	453	0	0
T11	0	23	0	0
T12	0	296	0	0
T13	0	82	0	0
T14	0	19	0	0
T15	0	161	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T18	1447	0	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166598932	23489	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	23489	0	0
T1	45255	23	0	0
T2	271886	159	0	0
T3	108227	78	0	0
T9	517783	873	0	0
T10	0	704	0	0
T11	0	39	0	0
T12	0	370	0	0
T13	0	140	0	0
T14	0	20	0	0
T15	0	273	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T18	1447	0	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0