Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
T23 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
3588166 |
522371 |
0 |
0 |
T5 |
142580 |
140660 |
0 |
0 |
T6 |
54104 |
52792 |
0 |
0 |
T7 |
69190 |
64812 |
0 |
0 |
T22 |
54176 |
50844 |
0 |
0 |
T23 |
153397 |
151826 |
0 |
0 |
T24 |
37640 |
32914 |
0 |
0 |
T25 |
425653 |
423179 |
0 |
0 |
T26 |
85902 |
82863 |
0 |
0 |
T27 |
96117 |
90614 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
999593592 |
985184292 |
0 |
14490 |
T4 |
834162 |
70770 |
0 |
18 |
T5 |
9972 |
9798 |
0 |
18 |
T6 |
12294 |
11952 |
0 |
18 |
T7 |
14958 |
13896 |
0 |
18 |
T22 |
12222 |
11400 |
0 |
18 |
T23 |
7350 |
7242 |
0 |
18 |
T24 |
8490 |
7338 |
0 |
18 |
T25 |
13650 |
13542 |
0 |
18 |
T26 |
19470 |
18720 |
0 |
18 |
T27 |
22002 |
20640 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T4 |
967624 |
82093 |
0 |
21 |
T5 |
51838 |
50997 |
0 |
21 |
T6 |
14469 |
14067 |
0 |
21 |
T7 |
19038 |
17687 |
0 |
21 |
T22 |
14599 |
13616 |
0 |
21 |
T23 |
57674 |
56925 |
0 |
21 |
T24 |
10145 |
8765 |
0 |
21 |
T25 |
165739 |
164567 |
0 |
21 |
T26 |
23077 |
22187 |
0 |
21 |
T27 |
25701 |
24111 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
194797 |
0 |
0 |
T1 |
0 |
252 |
0 |
0 |
T2 |
0 |
839 |
0 |
0 |
T3 |
0 |
722 |
0 |
0 |
T4 |
967624 |
84 |
0 |
0 |
T5 |
51838 |
123 |
0 |
0 |
T6 |
14469 |
95 |
0 |
0 |
T7 |
19038 |
78 |
0 |
0 |
T9 |
0 |
995 |
0 |
0 |
T10 |
0 |
420 |
0 |
0 |
T21 |
0 |
36 |
0 |
0 |
T22 |
14599 |
20 |
0 |
0 |
T23 |
57674 |
103 |
0 |
0 |
T24 |
10145 |
58 |
0 |
0 |
T25 |
165739 |
208 |
0 |
0 |
T26 |
23077 |
103 |
0 |
0 |
T27 |
25701 |
144 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
1786380 |
368449 |
0 |
0 |
T5 |
80770 |
79826 |
0 |
0 |
T6 |
27341 |
26734 |
0 |
0 |
T7 |
35194 |
33190 |
0 |
0 |
T22 |
27355 |
25789 |
0 |
0 |
T23 |
88373 |
87620 |
0 |
0 |
T24 |
19005 |
16772 |
0 |
0 |
T25 |
246264 |
245031 |
0 |
0 |
T26 |
43355 |
41917 |
0 |
0 |
T27 |
48414 |
45824 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420876966 |
416848243 |
0 |
0 |
T4 |
133462 |
11386 |
0 |
0 |
T5 |
9390 |
9242 |
0 |
0 |
T6 |
2007 |
1954 |
0 |
0 |
T7 |
2720 |
2530 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
10688 |
10554 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
31197 |
30980 |
0 |
0 |
T26 |
3211 |
3090 |
0 |
0 |
T27 |
3555 |
3338 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420876966 |
416841406 |
0 |
2415 |
T4 |
133462 |
11323 |
0 |
3 |
T5 |
9390 |
9239 |
0 |
3 |
T6 |
2007 |
1951 |
0 |
3 |
T7 |
2720 |
2527 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
10688 |
10551 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
31197 |
30977 |
0 |
3 |
T26 |
3211 |
3087 |
0 |
3 |
T27 |
3555 |
3335 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420876966 |
26993 |
0 |
0 |
T1 |
0 |
101 |
0 |
0 |
T2 |
0 |
355 |
0 |
0 |
T3 |
0 |
301 |
0 |
0 |
T4 |
133462 |
0 |
0 |
0 |
T5 |
9390 |
47 |
0 |
0 |
T6 |
2007 |
24 |
0 |
0 |
T7 |
2720 |
0 |
0 |
0 |
T9 |
0 |
420 |
0 |
0 |
T10 |
0 |
178 |
0 |
0 |
T21 |
0 |
15 |
0 |
0 |
T22 |
2037 |
0 |
0 |
0 |
T23 |
10688 |
36 |
0 |
0 |
T24 |
1415 |
12 |
0 |
0 |
T25 |
31197 |
0 |
0 |
0 |
T26 |
3211 |
0 |
0 |
0 |
T27 |
3555 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
16798 |
0 |
0 |
T1 |
0 |
68 |
0 |
0 |
T2 |
0 |
225 |
0 |
0 |
T3 |
0 |
188 |
0 |
0 |
T4 |
139027 |
0 |
0 |
0 |
T5 |
1662 |
17 |
0 |
0 |
T6 |
2049 |
3 |
0 |
0 |
T7 |
2493 |
0 |
0 |
0 |
T9 |
0 |
288 |
0 |
0 |
T10 |
0 |
110 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T22 |
2037 |
0 |
0 |
0 |
T23 |
1225 |
18 |
0 |
0 |
T24 |
1415 |
18 |
0 |
0 |
T25 |
2275 |
0 |
0 |
0 |
T26 |
3245 |
0 |
0 |
0 |
T27 |
3667 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
19124 |
0 |
0 |
T1 |
0 |
83 |
0 |
0 |
T2 |
0 |
259 |
0 |
0 |
T3 |
0 |
233 |
0 |
0 |
T4 |
139027 |
0 |
0 |
0 |
T5 |
1662 |
24 |
0 |
0 |
T6 |
2049 |
26 |
0 |
0 |
T7 |
2493 |
0 |
0 |
0 |
T9 |
0 |
287 |
0 |
0 |
T10 |
0 |
132 |
0 |
0 |
T21 |
0 |
11 |
0 |
0 |
T22 |
2037 |
0 |
0 |
0 |
T23 |
1225 |
19 |
0 |
0 |
T24 |
1415 |
6 |
0 |
0 |
T25 |
2275 |
0 |
0 |
0 |
T26 |
3245 |
0 |
0 |
0 |
T27 |
3667 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
448802225 |
0 |
0 |
T4 |
139027 |
79021 |
0 |
0 |
T5 |
9781 |
9712 |
0 |
0 |
T6 |
2091 |
2065 |
0 |
0 |
T7 |
2833 |
2764 |
0 |
0 |
T22 |
2122 |
2039 |
0 |
0 |
T23 |
11134 |
11093 |
0 |
0 |
T24 |
1475 |
1349 |
0 |
0 |
T25 |
32498 |
32400 |
0 |
0 |
T26 |
3344 |
3261 |
0 |
0 |
T27 |
3703 |
3563 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
448802225 |
0 |
0 |
T4 |
139027 |
79021 |
0 |
0 |
T5 |
9781 |
9712 |
0 |
0 |
T6 |
2091 |
2065 |
0 |
0 |
T7 |
2833 |
2764 |
0 |
0 |
T22 |
2122 |
2039 |
0 |
0 |
T23 |
11134 |
11093 |
0 |
0 |
T24 |
1475 |
1349 |
0 |
0 |
T25 |
32498 |
32400 |
0 |
0 |
T26 |
3344 |
3261 |
0 |
0 |
T27 |
3703 |
3563 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420876966 |
418846791 |
0 |
0 |
T4 |
133462 |
75841 |
0 |
0 |
T5 |
9390 |
9324 |
0 |
0 |
T6 |
2007 |
1982 |
0 |
0 |
T7 |
2720 |
2654 |
0 |
0 |
T22 |
2037 |
1957 |
0 |
0 |
T23 |
10688 |
10650 |
0 |
0 |
T24 |
1415 |
1294 |
0 |
0 |
T25 |
31197 |
31103 |
0 |
0 |
T26 |
3211 |
3131 |
0 |
0 |
T27 |
3555 |
3420 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420876966 |
418846791 |
0 |
0 |
T4 |
133462 |
75841 |
0 |
0 |
T5 |
9390 |
9324 |
0 |
0 |
T6 |
2007 |
1982 |
0 |
0 |
T7 |
2720 |
2654 |
0 |
0 |
T22 |
2037 |
1957 |
0 |
0 |
T23 |
10688 |
10650 |
0 |
0 |
T24 |
1415 |
1294 |
0 |
0 |
T25 |
31197 |
31103 |
0 |
0 |
T26 |
3211 |
3131 |
0 |
0 |
T27 |
3555 |
3420 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209898848 |
209898848 |
0 |
0 |
T4 |
37924 |
37924 |
0 |
0 |
T5 |
5206 |
5206 |
0 |
0 |
T6 |
1056 |
1056 |
0 |
0 |
T7 |
1327 |
1327 |
0 |
0 |
T22 |
979 |
979 |
0 |
0 |
T23 |
6214 |
6214 |
0 |
0 |
T24 |
678 |
678 |
0 |
0 |
T25 |
15552 |
15552 |
0 |
0 |
T26 |
1566 |
1566 |
0 |
0 |
T27 |
1710 |
1710 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209898848 |
209898848 |
0 |
0 |
T4 |
37924 |
37924 |
0 |
0 |
T5 |
5206 |
5206 |
0 |
0 |
T6 |
1056 |
1056 |
0 |
0 |
T7 |
1327 |
1327 |
0 |
0 |
T22 |
979 |
979 |
0 |
0 |
T23 |
6214 |
6214 |
0 |
0 |
T24 |
678 |
678 |
0 |
0 |
T25 |
15552 |
15552 |
0 |
0 |
T26 |
1566 |
1566 |
0 |
0 |
T27 |
1710 |
1710 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
104948810 |
104948810 |
0 |
0 |
T4 |
18962 |
18962 |
0 |
0 |
T5 |
2602 |
2602 |
0 |
0 |
T6 |
526 |
526 |
0 |
0 |
T7 |
664 |
664 |
0 |
0 |
T22 |
489 |
489 |
0 |
0 |
T23 |
3107 |
3107 |
0 |
0 |
T24 |
339 |
339 |
0 |
0 |
T25 |
7776 |
7776 |
0 |
0 |
T26 |
783 |
783 |
0 |
0 |
T27 |
855 |
855 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
104948810 |
104948810 |
0 |
0 |
T4 |
18962 |
18962 |
0 |
0 |
T5 |
2602 |
2602 |
0 |
0 |
T6 |
526 |
526 |
0 |
0 |
T7 |
664 |
664 |
0 |
0 |
T22 |
489 |
489 |
0 |
0 |
T23 |
3107 |
3107 |
0 |
0 |
T24 |
339 |
339 |
0 |
0 |
T25 |
7776 |
7776 |
0 |
0 |
T26 |
783 |
783 |
0 |
0 |
T27 |
855 |
855 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216351698 |
215326297 |
0 |
0 |
T4 |
66735 |
37921 |
0 |
0 |
T5 |
4695 |
4662 |
0 |
0 |
T6 |
1003 |
991 |
0 |
0 |
T7 |
1360 |
1327 |
0 |
0 |
T22 |
1018 |
979 |
0 |
0 |
T23 |
5344 |
5324 |
0 |
0 |
T24 |
708 |
648 |
0 |
0 |
T25 |
15599 |
15552 |
0 |
0 |
T26 |
1605 |
1566 |
0 |
0 |
T27 |
1777 |
1710 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216351698 |
215326297 |
0 |
0 |
T4 |
66735 |
37921 |
0 |
0 |
T5 |
4695 |
4662 |
0 |
0 |
T6 |
1003 |
991 |
0 |
0 |
T7 |
1360 |
1327 |
0 |
0 |
T22 |
1018 |
979 |
0 |
0 |
T23 |
5344 |
5324 |
0 |
0 |
T24 |
708 |
648 |
0 |
0 |
T25 |
15599 |
15552 |
0 |
0 |
T26 |
1605 |
1566 |
0 |
0 |
T27 |
1777 |
1710 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164197382 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
1662 |
1633 |
0 |
3 |
T6 |
2049 |
1992 |
0 |
3 |
T7 |
2493 |
2316 |
0 |
3 |
T22 |
2037 |
1900 |
0 |
3 |
T23 |
1225 |
1207 |
0 |
3 |
T24 |
1415 |
1223 |
0 |
3 |
T25 |
2275 |
2257 |
0 |
3 |
T26 |
3245 |
3120 |
0 |
3 |
T27 |
3667 |
3440 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166598932 |
164204377 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
1662 |
1636 |
0 |
0 |
T6 |
2049 |
1995 |
0 |
0 |
T7 |
2493 |
2319 |
0 |
0 |
T22 |
2037 |
1903 |
0 |
0 |
T23 |
1225 |
1210 |
0 |
0 |
T24 |
1415 |
1226 |
0 |
0 |
T25 |
2275 |
2260 |
0 |
0 |
T26 |
3245 |
3123 |
0 |
0 |
T27 |
3667 |
3443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446690219 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
9781 |
9623 |
0 |
3 |
T6 |
2091 |
2033 |
0 |
3 |
T7 |
2833 |
2632 |
0 |
3 |
T22 |
2122 |
1979 |
0 |
3 |
T23 |
11134 |
10990 |
0 |
3 |
T24 |
1475 |
1274 |
0 |
3 |
T25 |
32498 |
32269 |
0 |
3 |
T26 |
3344 |
3215 |
0 |
3 |
T27 |
3703 |
3474 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
33006 |
0 |
0 |
T4 |
139027 |
21 |
0 |
0 |
T5 |
9781 |
10 |
0 |
0 |
T6 |
2091 |
9 |
0 |
0 |
T7 |
2833 |
23 |
0 |
0 |
T22 |
2122 |
5 |
0 |
0 |
T23 |
11134 |
7 |
0 |
0 |
T24 |
1475 |
5 |
0 |
0 |
T25 |
32498 |
52 |
0 |
0 |
T26 |
3344 |
24 |
0 |
0 |
T27 |
3703 |
34 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446690219 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
9781 |
9623 |
0 |
3 |
T6 |
2091 |
2033 |
0 |
3 |
T7 |
2833 |
2632 |
0 |
3 |
T22 |
2122 |
1979 |
0 |
3 |
T23 |
11134 |
10990 |
0 |
3 |
T24 |
1475 |
1274 |
0 |
3 |
T25 |
32498 |
32269 |
0 |
3 |
T26 |
3344 |
3215 |
0 |
3 |
T27 |
3703 |
3474 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
32755 |
0 |
0 |
T4 |
139027 |
21 |
0 |
0 |
T5 |
9781 |
10 |
0 |
0 |
T6 |
2091 |
9 |
0 |
0 |
T7 |
2833 |
31 |
0 |
0 |
T22 |
2122 |
5 |
0 |
0 |
T23 |
11134 |
5 |
0 |
0 |
T24 |
1475 |
5 |
0 |
0 |
T25 |
32498 |
52 |
0 |
0 |
T26 |
3344 |
31 |
0 |
0 |
T27 |
3703 |
45 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446690219 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
9781 |
9623 |
0 |
3 |
T6 |
2091 |
2033 |
0 |
3 |
T7 |
2833 |
2632 |
0 |
3 |
T22 |
2122 |
1979 |
0 |
3 |
T23 |
11134 |
10990 |
0 |
3 |
T24 |
1475 |
1274 |
0 |
3 |
T25 |
32498 |
32269 |
0 |
3 |
T26 |
3344 |
3215 |
0 |
3 |
T27 |
3703 |
3474 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
33010 |
0 |
0 |
T4 |
139027 |
21 |
0 |
0 |
T5 |
9781 |
7 |
0 |
0 |
T6 |
2091 |
12 |
0 |
0 |
T7 |
2833 |
12 |
0 |
0 |
T22 |
2122 |
5 |
0 |
0 |
T23 |
11134 |
13 |
0 |
0 |
T24 |
1475 |
7 |
0 |
0 |
T25 |
32498 |
54 |
0 |
0 |
T26 |
3344 |
24 |
0 |
0 |
T27 |
3703 |
31 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446690219 |
0 |
2415 |
T4 |
139027 |
11795 |
0 |
3 |
T5 |
9781 |
9623 |
0 |
3 |
T6 |
2091 |
2033 |
0 |
3 |
T7 |
2833 |
2632 |
0 |
3 |
T22 |
2122 |
1979 |
0 |
3 |
T23 |
11134 |
10990 |
0 |
3 |
T24 |
1475 |
1274 |
0 |
3 |
T25 |
32498 |
32269 |
0 |
3 |
T26 |
3344 |
3215 |
0 |
3 |
T27 |
3703 |
3474 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
33111 |
0 |
0 |
T4 |
139027 |
21 |
0 |
0 |
T5 |
9781 |
8 |
0 |
0 |
T6 |
2091 |
12 |
0 |
0 |
T7 |
2833 |
12 |
0 |
0 |
T22 |
2122 |
5 |
0 |
0 |
T23 |
11134 |
5 |
0 |
0 |
T24 |
1475 |
5 |
0 |
0 |
T25 |
32498 |
50 |
0 |
0 |
T26 |
3344 |
24 |
0 |
0 |
T27 |
3703 |
34 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450942161 |
446697093 |
0 |
0 |
T4 |
139027 |
11878 |
0 |
0 |
T5 |
9781 |
9626 |
0 |
0 |
T6 |
2091 |
2036 |
0 |
0 |
T7 |
2833 |
2635 |
0 |
0 |
T22 |
2122 |
1982 |
0 |
0 |
T23 |
11134 |
10993 |
0 |
0 |
T24 |
1475 |
1277 |
0 |
0 |
T25 |
32498 |
32272 |
0 |
0 |
T26 |
3344 |
3218 |
0 |
0 |
T27 |
3703 |
3477 |
0 |
0 |