Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	166598932	164077672	0	0
AllClkBypReqTrue_A	166598932	124426	0	0
IoClkBypReqFalse_A	166598932	164000727	0	2415
IoClkBypReqTrue_A	166598932	196813	0	0
LcClkBypAckFalse_A	166598932	164084973	0	0
LcClkBypAckTrue_A	166598932	117125	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	164077672	0	0
T4	139027	11857	0	0
T5	1662	1450	0	0
T6	2049	1835	0	0
T7	2493	2318	0	0
T22	2037	1902	0	0
T23	1225	1111	0	0
T24	1415	1192	0	0
T25	2275	2259	0	0
T26	3245	3122	0	0
T27	3667	3442	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	124426	0	0
T1	0	453	0	0
T2	0	1623	0	0
T3	0	2037	0	0
T4	139027	0	0	0
T5	1662	185	0	0
T6	2049	159	0	0
T7	2493	0	0	0
T9	0	2512	0	0
T10	0	1303	0	0
T21	0	142	0	0
T22	2037	0	0	0
T23	1225	98	0	0
T24	1415	33	0	0
T25	2275	0	0	0
T26	3245	0	0	0
T27	3667	0	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	164000727	0	2415
T4	139027	11815	0	3
T5	1662	1393	0	3
T6	2049	1959	0	3
T7	2493	2316	0	3
T22	2037	1900	0	3
T23	1225	1024	0	3
T24	1415	1132	0	3
T25	2275	2257	0	3
T26	3245	3120	0	3
T27	3667	3440	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	196813	0	0
T1	0	612	0	0
T2	0	2766	0	0
T3	0	2901	0	0
T4	139027	0	0	0
T5	1662	240	0	0
T6	2049	33	0	0
T7	2493	0	0	0
T9	0	4802	0	0
T10	0	1730	0	0
T21	0	154	0	0
T22	2037	0	0	0
T23	1225	183	0	0
T24	1415	91	0	0
T25	2275	0	0	0
T26	3245	0	0	0
T27	3667	0	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	164084973	0	0
T4	139027	11857	0	0
T5	1662	1472	0	0
T6	2049	1962	0	0
T7	2493	2318	0	0
T22	2037	1902	0	0
T23	1225	1055	0	0
T24	1415	1178	0	0
T25	2275	2259	0	0
T26	3245	3122	0	0
T27	3667	3442	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	117125	0	0
T1	0	402	0	0
T2	0	1615	0	0
T3	0	1748	0	0
T4	139027	0	0	0
T5	1662	163	0	0
T6	2049	32	0	0
T7	2493	0	0	0
T9	0	2352	0	0
T10	0	923	0	0
T21	0	94	0	0
T22	2037	0	0	0
T23	1225	154	0	0
T24	1415	47	0	0
T25	2275	0	0	0
T26	3245	0	0	0
T27	3667	0	0	0