Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1803770332	16530	0	0
TransStop_A	1803770332	8674	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1803770332	16530	0	0
T1	822848	70	0	0
T2	0	177	0	0
T4	556112	0	0	0
T7	11336	20	0	0
T16	0	4	0	0
T17	0	34	0	0
T18	0	10	0	0
T22	8492	4	0	0
T23	44536	0	0	0
T24	5904	0	0	0
T25	129996	31	0	0
T26	13380	34	0	0
T27	14816	39	0	0
T35	5624	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1803770332	8674	0	0
T1	822848	36	0	0
T2	0	100	0	0
T3	0	45	0	0
T4	556112	0	0	0
T7	11336	8	0	0
T16	0	4	0	0
T17	0	21	0	0
T18	0	1	0	0
T22	8492	4	0	0
T23	44536	0	0	0
T24	5904	0	0	0
T25	129996	17	0	0
T26	13380	18	0	0
T27	14816	13	0	0
T35	5624	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	450942583	4152	0	0
TransStop_A	450942583	2204	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	4152	0	0
T1	205712	20	0	0
T2	0	45	0	0
T4	139028	0	0	0
T7	2834	5	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	3	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	7	0	0
T26	3345	10	0	0
T27	3704	7	0	0
T35	1406	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	2204	0	0
T1	205712	10	0	0
T2	0	24	0	0
T3	0	15	0	0
T4	139028	0	0	0
T7	2834	1	0	0
T16	0	1	0	0
T17	0	7	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	3	0	0
T26	3345	6	0	0
T27	3704	4	0	0
T35	1406	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	450942583	4088	0	0
TransStop_A	450942583	2123	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	4088	0	0
T1	205712	16	0	0
T2	0	40	0	0
T4	139028	0	0	0
T7	2834	5	0	0
T16	0	1	0	0
T17	0	8	0	0
T18	0	3	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	7	0	0
T26	3345	9	0	0
T27	3704	9	0	0
T35	1406	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	2123	0	0
T1	205712	7	0	0
T2	0	23	0	0
T4	139028	0	0	0
T7	2834	3	0	0
T16	0	1	0	0
T17	0	6	0	0
T18	0	1	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	4	0	0
T26	3345	4	0	0
T27	3704	3	0	0
T35	1406	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	450942583	4118	0	0
TransStop_A	450942583	2169	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	4118	0	0
T1	205712	18	0	0
T2	0	47	0	0
T4	139028	0	0	0
T7	2834	6	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	3	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	7	0	0
T26	3345	8	0	0
T27	3704	10	0	0
T35	1406	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	2169	0	0
T1	205712	9	0	0
T2	0	27	0	0
T3	0	17	0	0
T4	139028	0	0	0
T7	2834	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	5	0	0
T26	3345	5	0	0
T27	3704	3	0	0
T35	1406	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	450942583	4172	0	0
TransStop_A	450942583	2178	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	4172	0	0
T1	205712	16	0	0
T2	0	45	0	0
T4	139028	0	0	0
T7	2834	4	0	0
T16	0	1	0	0
T17	0	11	0	0
T18	0	1	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	10	0	0
T26	3345	7	0	0
T27	3704	13	0	0
T35	1406	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942583	2178	0	0
T1	205712	10	0	0
T2	0	26	0	0
T3	0	13	0	0
T4	139028	0	0	0
T7	2834	2	0	0
T16	0	1	0	0
T17	0	6	0	0
T22	2123	1	0	0
T23	11134	0	0	0
T24	1476	0	0	0
T25	32499	5	0	0
T26	3345	3	0	0
T27	3704	3	0	0
T35	1406	0	0	0