Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	167471629	5691704	0	0
clk_enables_rd_A	167471629	46900	0	0
clk_hints_rd_A	167471629	41172	0	0
extclk_ctrl_rd_A	167471629	53563	0	0
extclk_ctrl_regwen_rd_A	167471629	40598	0	0
jitter_enable_rd_A	167471629	60537	0	0
jitter_regwen_rd_A	167471629	44873	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	5691704	0	0
T2	271886	99650	0	0
T3	108227	31153	0	0
T9	517783	153293	0	0
T10	307701	109243	0	0
T11	74026	0	0	0
T12	0	193200	0	0
T15	0	64350	0	0
T19	1283	0	0	0
T20	657	0	0	0
T21	1492	0	0	0
T29	0	54246	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T69	0	59358	0	0
T70	0	188478	0	0
T71	0	47718	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	46900	0	0
T3	108227	1321	0	0
T9	517783	5778	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T21	1492	0	0	0
T28	0	4	0	0
T29	0	2232	0	0
T30	2389	0	0	0
T31	226429	7	0	0
T32	38733	0	0	0
T36	925	0	0	0
T71	0	1763	0	0
T127	0	8	0	0
T128	0	5	0	0
T129	0	7	0	0
T130	0	1293	0	0
T131	1621	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	41172	0	0
T3	108227	1145	0	0
T9	517783	5363	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T21	1492	0	0	0
T28	0	2	0	0
T29	0	1696	0	0
T30	2389	0	0	0
T31	226429	11	0	0
T32	38733	0	0	0
T36	925	0	0	0
T71	0	1752	0	0
T127	0	7	0	0
T128	0	1	0	0
T129	0	8	0	0
T130	0	1200	0	0
T131	1621	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	53563	0	0
T3	0	1485	0	0
T4	139027	144	0	0
T6	2049	37	0	0
T7	2493	0	0	0
T9	0	6590	0	0
T21	0	8	0	0
T22	2037	0	0	0
T23	1225	0	0	0
T24	1415	0	0	0
T25	2275	0	0	0
T26	3245	0	0	0
T27	3667	0	0	0
T28	0	81	0	0
T31	0	92	0	0
T35	1405	0	0	0
T132	0	14	0	0
T133	0	27	0	0
T134	0	4	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	40598	0	0
T1	45255	0	0	0
T3	0	1163	0	0
T4	139027	63	0	0
T9	0	5140	0	0
T16	1525	0	0	0
T17	2696	0	0	0
T23	1225	0	0	0
T24	1415	0	0	0
T25	2275	0	0	0
T26	3245	0	0	0
T27	3667	0	0	0
T29	0	1932	0	0
T35	1405	0	0	0
T71	0	1672	0	0
T106	0	30	0	0
T107	0	37	0	0
T130	0	1228	0	0
T135	0	61	0	0
T136	0	1746	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	60537	0	0
T3	108227	1986	0	0
T9	517783	8067	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T21	1492	0	0	0
T28	0	146	0	0
T29	0	2212	0	0
T30	2389	0	0	0
T31	226429	199	0	0
T32	38733	0	0	0
T36	925	0	0	0
T71	0	1812	0	0
T127	0	108	0	0
T128	0	108	0	0
T129	0	122	0	0
T130	0	1813	0	0
T131	1621	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167471629	44873	0	0
T3	108227	1189	0	0
T9	517783	5858	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T21	1492	0	0	0
T29	0	2243	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T32	38733	0	0	0
T36	925	0	0	0
T71	0	1680	0	0
T130	0	1554	0	0
T131	1621	0	0	0
T136	0	1891	0	0
T137	0	2688	0	0
T138	0	5328	0	0
T139	0	876	0	0
T140	0	1507	0	0