Module Definition
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Module : prim_generic_flop_2sync
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_2sync_0/rtl/prim_generic_flop_2sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_main_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic
tb.dut.u_main_status.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_io_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic
tb.dut.u_io_status.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_usb_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic
tb.dut.u_usb_status.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_meas.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_meas.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div2_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_io_div4_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_main_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_usb_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic
tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic



Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_meas_ctrl_shadowed_hi_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_meas_ctrl_shadowed_lo_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_meas_ctrl_shadowed_hi_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_meas_ctrl_shadowed_lo_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_meas_ctrl_shadowed_hi_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_meas_ctrl_shadowed_lo_err_storage_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_status.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_status.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_root_ctrl.u_cg.i_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_status.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_ref_meas_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_ref_meas_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_ref_meas_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_ref_meas_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_ref_meas_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref.prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_timeout_err_sync.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_div4_peri_sw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_div2_peri_sw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_peri_sw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_usb_peri_sw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_hint_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_err_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_hint_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_err_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_hint_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_err_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_hint_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_err_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00

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