Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	499796796	396	0	0
StatusRise_A	499796796	396	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499796796	396	0	0
T3	324681	0	0	0
T9	1553349	0	0	0
T10	923103	0	0	0
T11	222078	0	0	0
T19	3849	6	0	0
T20	1971	0	0	0
T21	4476	0	0	0
T30	7167	0	0	0
T31	679287	0	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	12	0	0
T131	4863	0	0	0
T141	0	2	0	0
T142	0	10	0	0
T143	0	9	0	0
T144	0	15	0	0
T145	0	3	0	0
T146	0	5	0	0
T147	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499796796	396	0	0
T3	324681	0	0	0
T9	1553349	0	0	0
T10	923103	0	0	0
T11	222078	0	0	0
T19	3849	6	0	0
T20	1971	0	0	0
T21	4476	0	0	0
T30	7167	0	0	0
T31	679287	0	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	12	0	0
T131	4863	0	0	0
T141	0	2	0	0
T142	0	10	0	0
T143	0	9	0	0
T144	0	15	0	0
T145	0	3	0	0
T146	0	5	0	0
T147	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166598932	133	0	0
StatusRise_A	166598932	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	133	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	1	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	133	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	1	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166598932	144	0	0
StatusRise_A	166598932	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	144	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	2	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0
T146	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	144	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	2	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0
T146	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166598932	119	0	0
StatusRise_A	166598932	119	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	119	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	3	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	3	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166598932	119	0	0
T3	108227	0	0	0
T9	517783	0	0	0
T10	307701	0	0	0
T11	74026	0	0	0
T19	1283	3	0	0
T20	657	0	0	0
T21	1492	0	0	0
T30	2389	0	0	0
T31	226429	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1621	0	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	3	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	5	0	0