Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48133	0	0
CgEnOn_A	2147483647	38996	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48133	0	0
T1	0	20	0	0
T3	1367109	0	0	0
T4	329375	63	0	0
T5	17198	3	0	0
T6	3589	3	0	0
T7	7544	8	0	0
T9	1082144	0	0	0
T10	1224435	0	0	0
T11	171900	0	0	0
T19	2566	10	0	0
T20	17723	0	0	0
T21	3187	0	0	0
T22	5627	7	0	0
T23	31143	3	0	0
T24	3907	3	0	0
T25	87023	10	0	0
T26	8904	13	0	0
T27	9823	10	0	0
T30	5621	0	0	0
T31	895938	0	0	0
T35	1405	0	0	0
T42	0	5	0	0
T43	0	5	0	0
T44	0	20	0	0
T70	0	5	0	0
T131	6994	0	0	0
T141	0	5	0	0
T142	0	20	0	0
T143	0	20	0	0
T144	0	30	0	0
T145	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38996	0	0
T1	553102	0	0	0
T2	0	318	0	0
T3	1367109	105	0	0
T4	329375	0	0	0
T7	2833	0	0	0
T9	1082144	383	0	0
T10	1224435	289	0	0
T11	171900	0	0	0
T16	2629	1	0	0
T19	2566	16	0	0
T20	17723	6	0	0
T21	3187	0	0	0
T22	5627	3	0	0
T23	31143	0	0	0
T24	3907	0	0	0
T25	87023	0	0	0
T26	8904	0	0	0
T27	9823	0	0	0
T30	5621	0	0	0
T31	895938	43	0	0
T35	3665	0	0	0
T42	0	5	0	0
T43	0	5	0	0
T44	0	20	0	0
T70	0	4	0	0
T131	6994	3	0	0
T141	0	5	0	0
T142	0	20	0	0
T143	0	20	0	0
T144	0	30	0	0
T145	0	5	0	0
T146	0	2	0	0
T148	0	31	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209898848	151	0	0
CgEnOn_A	209898848	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209898848	151	0	0
T3	506370	0	0	0
T9	240104	0	0	0
T10	271669	0	0	0
T11	38195	0	0	0
T19	549	2	0	0
T20	3930	0	0	0
T21	702	0	0	0
T30	1297	0	0	0
T31	199304	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	1527	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209898848	151	0	0
T3	506370	0	0	0
T9	240104	0	0	0
T10	271669	0	0	0
T11	38195	0	0	0
T19	549	2	0	0
T20	3930	0	0	0
T21	702	0	0	0
T30	1297	0	0	0
T31	199304	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	1527	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104948810	151	0	0
CgEnOn_A	104948810	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104948810	151	0	0
CgEnOn_A	104948810	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104948810	151	0	0
CgEnOn_A	104948810	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	151	0	0
T3	253184	0	0	0
T9	120051	0	0	0
T10	135834	0	0	0
T11	19097	0	0	0
T19	275	2	0	0
T20	1965	0	0	0
T21	351	0	0	0
T30	645	0	0	0
T31	99653	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	764	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	420876966	151	0	0
CgEnOn_A	420876966	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420876966	151	0	0
T3	101187	0	0	0
T9	481887	0	0	0
T10	545264	0	0	0
T11	76414	0	0	0
T19	1192	2	0	0
T20	7898	0	0	0
T21	1432	0	0	0
T30	2389	0	0	0
T31	397675	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T70	0	1	0	0
T131	3175	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420876966	145	0	0
T3	101187	0	0	0
T9	481887	0	0	0
T10	545264	0	0	0
T11	76414	0	0	0
T19	1192	2	0	0
T20	7898	0	0	0
T21	1432	0	0	0
T30	2389	0	0	0
T31	397675	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	3175	0	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	139	0	0
CgEnOn_A	450942161	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	139	0	0
T3	107027	0	0	0
T9	522382	0	0	0
T10	606402	0	0	0
T11	79600	0	0	0
T19	1245	1	0	0
T20	8227	0	0	0
T21	1492	0	0	0
T29	0	1	0	0
T30	2490	0	0	0
T31	516259	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	3308	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	134	0	0
T3	107027	0	0	0
T9	522382	0	0	0
T10	606402	0	0	0
T11	79600	0	0	0
T19	1245	1	0	0
T20	8227	0	0	0
T21	1492	0	0	0
T30	2490	0	0	0
T31	516259	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	3308	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	139	0	0
CgEnOn_A	450942161	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	139	0	0
T3	107027	0	0	0
T9	522382	0	0	0
T10	606402	0	0	0
T11	79600	0	0	0
T19	1245	1	0	0
T20	8227	0	0	0
T21	1492	0	0	0
T29	0	1	0	0
T30	2490	0	0	0
T31	516259	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	3308	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	134	0	0
T3	107027	0	0	0
T9	522382	0	0	0
T10	606402	0	0	0
T11	79600	0	0	0
T19	1245	1	0	0
T20	8227	0	0	0
T21	1492	0	0	0
T30	2490	0	0	0
T31	516259	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	3308	0	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216351698	119	0	0
CgEnOn_A	216351698	119	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216351698	119	0	0
T3	515754	0	0	0
T9	251899	0	0	0
T10	288197	0	0	0
T11	38209	0	0	0
T19	596	3	0	0
T20	3949	0	0	0
T21	716	0	0	0
T30	1195	0	0	0
T31	236288	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1588	0	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	3	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216351698	119	0	0
T3	515754	0	0	0
T9	251899	0	0	0
T10	288197	0	0	0
T11	38209	0	0	0
T19	596	3	0	0
T20	3949	0	0	0
T21	716	0	0	0
T30	1195	0	0	0
T31	236288	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T131	1588	0	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	3	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T42,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104948810	7437	0	0
CgEnOn_A	104948810	5165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	7437	0	0
T4	18962	21	0	0
T5	2602	1	0	0
T6	526	1	0	0
T7	664	1	0	0
T22	489	2	0	0
T23	3107	1	0	0
T24	339	1	0	0
T25	7776	1	0	0
T26	783	1	0	0
T27	855	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948810	5165	0	0
T1	49969	0	0	0
T2	0	107	0	0
T3	0	36	0	0
T4	18962	0	0	0
T9	0	126	0	0
T10	0	95	0	0
T16	368	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T22	489	1	0	0
T23	3107	0	0	0
T24	339	0	0	0
T25	7776	0	0	0
T26	783	0	0	0
T27	855	0	0	0
T31	0	13	0	0
T35	304	0	0	0
T131	0	1	0	0
T148	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T42,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209898848	7462	0	0
CgEnOn_A	209898848	5190	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209898848	7462	0	0
T4	37924	21	0	0
T5	5206	1	0	0
T6	1056	1	0	0
T7	1327	1	0	0
T22	979	2	0	0
T23	6214	1	0	0
T24	678	1	0	0
T25	15552	1	0	0
T26	1566	1	0	0
T27	1710	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209898848	5190	0	0
T1	99946	0	0	0
T2	0	105	0	0
T3	0	34	0	0
T4	37924	0	0	0
T9	0	128	0	0
T10	0	97	0	0
T16	736	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T22	979	1	0	0
T23	6214	0	0	0
T24	678	0	0	0
T25	15552	0	0	0
T26	1566	0	0	0
T27	1710	0	0	0
T31	0	14	0	0
T35	607	0	0	0
T131	0	1	0	0
T148	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T42,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	420876966	7507	0	0
CgEnOn_A	420876966	5229	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420876966	7507	0	0
T4	133462	21	0	0
T5	9390	1	0	0
T6	2007	1	0	0
T7	2720	1	0	0
T22	2037	2	0	0
T23	10688	1	0	0
T24	1415	1	0	0
T25	31197	1	0	0
T26	3211	1	0	0
T27	3555	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420876966	5229	0	0
T1	197476	0	0	0
T2	0	106	0	0
T3	0	35	0	0
T4	133462	0	0	0
T9	0	129	0	0
T10	0	97	0	0
T16	1525	1	0	0
T19	0	2	0	0
T20	0	2	0	0
T22	2037	1	0	0
T23	10688	0	0	0
T24	1415	0	0	0
T25	31197	0	0	0
T26	3211	0	0	0
T27	3555	0	0	0
T31	0	16	0	0
T35	1349	0	0	0
T131	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T43,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216351698	7489	0	0
CgEnOn_A	216351698	5210	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216351698	7489	0	0
T4	66735	21	0	0
T5	4695	1	0	0
T6	1003	1	0	0
T7	1360	1	0	0
T22	1018	2	0	0
T23	5344	1	0	0
T24	708	1	0	0
T25	15599	1	0	0
T26	1605	1	0	0
T27	1777	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216351698	5210	0	0
T1	98742	0	0	0
T2	0	111	0	0
T3	0	33	0	0
T4	66735	0	0	0
T9	0	124	0	0
T10	0	96	0	0
T16	762	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	1018	1	0	0
T23	5344	0	0	0
T24	708	0	0	0
T25	15599	0	0	0
T26	1605	0	0	0
T27	1777	0	0	0
T31	0	15	0	0
T35	675	0	0	0
T131	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T22,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	4291	0	0
CgEnOn_A	450942161	4286	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4291	0	0
T1	205711	20	0	0
T2	0	45	0	0
T4	139027	0	0	0
T7	2833	5	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	10	0	0
T27	3703	7	0	0
T35	1405	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4286	0	0
T1	205711	20	0	0
T2	0	45	0	0
T4	139027	0	0	0
T7	2833	5	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	10	0	0
T27	3703	7	0	0
T35	1405	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T22,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	4227	0	0
CgEnOn_A	450942161	4222	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4227	0	0
T1	205711	16	0	0
T2	0	40	0	0
T4	139027	0	0	0
T7	2833	5	0	0
T16	0	1	0	0
T17	0	8	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	9	0	0
T27	3703	9	0	0
T35	1405	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4222	0	0
T1	205711	16	0	0
T2	0	40	0	0
T4	139027	0	0	0
T7	2833	5	0	0
T16	0	1	0	0
T17	0	8	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	9	0	0
T27	3703	9	0	0
T35	1405	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T22,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	4257	0	0
CgEnOn_A	450942161	4252	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4257	0	0
T1	205711	18	0	0
T2	0	47	0	0
T4	139027	0	0	0
T7	2833	6	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	8	0	0
T27	3703	10	0	0
T35	1405	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4252	0	0
T1	205711	18	0	0
T2	0	47	0	0
T4	139027	0	0	0
T7	2833	6	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	3	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	7	0	0
T26	3344	8	0	0
T27	3703	10	0	0
T35	1405	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T22,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	450942161	4311	0	0
CgEnOn_A	450942161	4306	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4311	0	0
T1	205711	16	0	0
T2	0	45	0	0
T4	139027	0	0	0
T7	2833	4	0	0
T16	0	1	0	0
T17	0	11	0	0
T18	0	1	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	10	0	0
T26	3344	7	0	0
T27	3703	13	0	0
T35	1405	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450942161	4306	0	0
T1	205711	16	0	0
T2	0	45	0	0
T4	139027	0	0	0
T7	2833	4	0	0
T16	0	1	0	0
T17	0	11	0	0
T18	0	1	0	0
T22	2122	1	0	0
T23	11134	0	0	0
T24	1475	0	0	0
T25	32498	10	0	0
T26	3344	7	0	0
T27	3703	13	0	0
T35	1405	0	0	0