Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	631644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3654754

1

T4

39

T5

10

T6

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1051028	1			T4	64		T5	9		T6	30
values[0x0]	1485786	1			T4	19		T5	5		T6	15
values[0x1]	1749584	1			T4	29		T5	14		T6	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	345933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3940465

1

T4

50

T5

11

T6

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18160	1			T4	2		T1	288		T27	3
valid_sources[0x01]	16388	1			T1	237		T2	4		T17	1
valid_sources[0x02]	16647	1			T1	245		T2	1		T27	5
valid_sources[0x03]	15373	1			T4	2		T1	257		T2	25
valid_sources[0x04]	17396	1			T4	1		T1	237		T65	2
valid_sources[0x05]	18486	1			T4	1		T1	307		T27	5
valid_sources[0x06]	18300	1			T1	226		T2	2		T9	3
valid_sources[0x07]	16365	1			T6	1		T1	260		T18	119
valid_sources[0x08]	17436	1			T4	1		T1	226		T9	1
valid_sources[0x09]	18247	1			T4	3		T1	253		T17	1
valid_sources[0x0a]	16964	1			T4	1		T6	1		T1	271
valid_sources[0x0b]	15219	1			T4	2		T1	287		T2	6
valid_sources[0x0c]	15863	1			T1	284		T27	2		T9	3
valid_sources[0x0d]	15955	1			T4	1		T1	253		T2	30
valid_sources[0x0e]	17951	1			T4	2		T1	336		T2	6
valid_sources[0x0f]	16111	1			T4	1		T5	1		T1	232
valid_sources[0x10]	15813	1			T1	248		T65	1		T3	2
valid_sources[0x11]	17045	1			T1	240		T27	5		T9	5
valid_sources[0x12]	17490	1			T1	247		T2	3		T17	2
valid_sources[0x13]	17813	1			T1	265		T2	4		T3	2
valid_sources[0x14]	16410	1			T1	263		T2	13		T17	2
valid_sources[0x15]	16301	1			T1	214		T2	14		T27	1
valid_sources[0x16]	17574	1			T5	1		T1	275		T2	16
valid_sources[0x17]	17837	1			T5	1		T1	175		T2	1
valid_sources[0x18]	16348	1			T4	2		T1	251		T2	12
valid_sources[0x19]	17177	1			T1	300		T2	26		T9	2
valid_sources[0x1a]	15352	1			T1	253		T2	6		T3	1
valid_sources[0x1b]	15526	1			T5	1		T1	269		T27	2
valid_sources[0x1c]	16889	1			T4	2		T1	239		T2	6
valid_sources[0x1d]	16152	1			T4	1		T6	1		T1	269
valid_sources[0x1e]	17018	1			T1	264		T2	1		T3	2
valid_sources[0x1f]	17348	1			T1	273		T17	1		T65	1
valid_sources[0x20]	16724	1			T1	282		T2	8		T27	2
valid_sources[0x21]	16870	1			T4	1		T1	300		T2	3
valid_sources[0x22]	14678	1			T4	1		T1	237		T2	1
valid_sources[0x23]	16596	1			T4	4		T1	239		T2	7
valid_sources[0x24]	15964	1			T6	1		T1	307		T2	1
valid_sources[0x25]	16142	1			T6	1		T1	298		T27	2
valid_sources[0x26]	17311	1			T1	263		T2	4		T27	7
valid_sources[0x27]	15869	1			T1	292		T27	1		T9	5
valid_sources[0x28]	15961	1			T4	2		T1	258		T17	2
valid_sources[0x29]	16339	1			T1	253		T2	5		T3	1
valid_sources[0x2a]	16642	1			T1	242		T27	4		T9	5
valid_sources[0x2b]	16373	1			T4	1		T1	262		T2	8
valid_sources[0x2c]	17055	1			T1	228		T2	19		T27	2
valid_sources[0x2d]	15467	1			T4	2		T1	228		T2	1
valid_sources[0x2e]	17771	1			T1	251		T2	11		T9	8
valid_sources[0x2f]	16490	1			T1	190		T3	2		T9	4
valid_sources[0x30]	15245	1			T1	284		T2	4		T3	5
valid_sources[0x31]	17258	1			T1	260		T2	5		T16	1
valid_sources[0x32]	16257	1			T4	1		T1	264		T27	1
valid_sources[0x33]	15984	1			T1	272		T2	12		T9	2
valid_sources[0x34]	16388	1			T6	2		T1	280		T65	1
valid_sources[0x35]	16547	1			T1	257		T27	11		T9	6
valid_sources[0x36]	15745	1			T1	286		T17	1		T22	5
valid_sources[0x37]	17682	1			T1	292		T27	5		T9	2
valid_sources[0x38]	14636	1			T1	296		T22	1		T27	3
valid_sources[0x39]	17405	1			T4	1		T1	246		T2	9
valid_sources[0x3a]	16341	1			T5	1		T1	291		T2	50
valid_sources[0x3b]	15740	1			T5	1		T1	276		T17	11
valid_sources[0x3c]	16452	1			T1	268		T2	6		T17	5
valid_sources[0x3d]	15580	1			T4	1		T1	205		T2	27
valid_sources[0x3e]	15491	1			T4	3		T1	312		T2	11
valid_sources[0x3f]	16558	1			T1	263		T2	4		T27	1
valid_sources[0x40]	17634	1			T1	255		T2	10		T3	1
valid_sources[0x41]	14546	1			T5	1		T1	266		T2	9
valid_sources[0x42]	16530	1			T5	1		T1	237		T2	2
valid_sources[0x43]	16322	1			T4	1		T6	1		T1	246
valid_sources[0x44]	18257	1			T1	236		T2	2		T22	2
valid_sources[0x45]	17904	1			T1	272		T2	12		T27	2
valid_sources[0x46]	16468	1			T1	263		T27	1		T9	1
valid_sources[0x47]	16186	1			T4	2		T1	329		T22	2
valid_sources[0x48]	16894	1			T6	1		T1	176		T27	1
valid_sources[0x49]	16064	1			T4	1		T1	283		T17	4
valid_sources[0x4a]	16512	1			T1	271		T2	5		T3	1
valid_sources[0x4b]	16042	1			T6	1		T1	254		T27	2
valid_sources[0x4c]	18892	1			T5	1		T1	273		T2	4
valid_sources[0x4d]	17262	1			T6	1		T1	186		T16	1
valid_sources[0x4e]	17907	1			T1	279		T2	14		T17	1
valid_sources[0x4f]	16091	1			T5	2		T1	265		T2	13
valid_sources[0x50]	17339	1			T1	301		T2	8		T23	1
valid_sources[0x51]	17380	1			T1	229		T16	1		T98	12
valid_sources[0x52]	17210	1			T1	255		T2	1		T3	3
valid_sources[0x53]	16685	1			T1	265		T2	4		T3	1
valid_sources[0x54]	18908	1			T1	239		T2	4		T17	3
valid_sources[0x55]	16288	1			T1	229		T97	1		T9	3
valid_sources[0x56]	14532	1			T5	1		T1	262		T3	1
valid_sources[0x57]	15324	1			T1	227		T2	16		T17	1
valid_sources[0x58]	16482	1			T4	2		T1	279		T2	5
valid_sources[0x59]	16320	1			T1	227		T2	6		T17	2
valid_sources[0x5a]	17502	1			T1	211		T27	1		T9	2
valid_sources[0x5b]	17261	1			T5	1		T6	1		T1	229
valid_sources[0x5c]	16530	1			T6	2		T1	287		T2	38
valid_sources[0x5d]	16862	1			T1	284		T27	4		T9	2
valid_sources[0x5e]	17184	1			T4	1		T1	206		T27	3
valid_sources[0x5f]	16323	1			T1	240		T2	20		T9	5
valid_sources[0x60]	16828	1			T4	1		T6	1		T1	288
valid_sources[0x61]	16013	1			T1	203		T2	16		T27	1
valid_sources[0x62]	16372	1			T1	224		T16	1		T3	1
valid_sources[0x63]	16641	1			T4	1		T1	271		T2	4
valid_sources[0x64]	16192	1			T1	284		T2	28		T3	1
valid_sources[0x65]	17466	1			T6	1		T1	300		T16	1
valid_sources[0x66]	16268	1			T6	1		T1	274		T27	1
valid_sources[0x67]	16394	1			T1	266		T2	11		T22	2
valid_sources[0x68]	17448	1			T1	349		T2	3		T3	1
valid_sources[0x69]	17159	1			T1	293		T2	10		T16	3
valid_sources[0x6a]	16629	1			T1	212		T2	1		T3	2
valid_sources[0x6b]	16742	1			T1	253		T27	5		T9	7
valid_sources[0x6c]	15777	1			T1	311		T2	7		T17	1
valid_sources[0x6d]	17153	1			T1	295		T27	4		T9	5
valid_sources[0x6e]	16076	1			T1	265		T2	14		T3	3
valid_sources[0x6f]	16158	1			T4	1		T5	1		T1	235
valid_sources[0x70]	16818	1			T1	227		T2	10		T3	1
valid_sources[0x71]	18209	1			T6	1		T1	298		T2	6
valid_sources[0x72]	15245	1			T4	1		T1	230		T3	1
valid_sources[0x73]	16661	1			T4	1		T6	2		T1	246
valid_sources[0x74]	16166	1			T4	4		T1	269		T17	2
valid_sources[0x75]	18011	1			T1	296		T2	9		T17	4
valid_sources[0x76]	17796	1			T1	237		T16	1		T22	1
valid_sources[0x77]	16915	1			T1	270		T3	1		T27	1
valid_sources[0x78]	18086	1			T4	1		T1	246		T3	1
valid_sources[0x79]	17028	1			T1	267		T2	1		T27	3
valid_sources[0x7a]	18121	1			T4	3		T1	250		T16	1
valid_sources[0x7b]	16788	1			T1	239		T2	19		T23	4
valid_sources[0x7c]	15753	1			T1	251		T2	11		T27	2
valid_sources[0x7d]	17704	1			T4	1		T1	295		T3	1
valid_sources[0x7e]	17370	1			T4	2		T1	243		T3	1
valid_sources[0x7f]	16175	1			T1	284		T2	1		T27	2
valid_sources[0x80]	16853	1			T1	359		T2	2		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

920435

1

T4

26

T5

6

T6

20

values[0x0]

all_enables

biggest_size

1391166

1

T4

7

T5

3

T6

3

values[0x1]

all_enables

biggest_size

1343153

1

T4

6

T5

1

T6

5