Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	991152489	13958	0	0
GateOpen_A	991152489	20952	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991152489	13958	0	0
T1	1724527	227	0	0
T2	1175778	8	0	0
T3	0	14	0	0
T9	0	86	0	0
T16	12450	0	0	0
T17	18769	4	0	0
T18	6982	0	0	0
T19	10547	17	0	0
T20	3300	5	0	0
T21	3417	21	0	0
T22	6085	0	0	0
T23	39240	0	0	0
T66	0	16	0	0
T99	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991152489	20952	0	0
T1	1724527	243	0	0
T2	1175778	24	0	0
T4	6386	4	0	0
T5	4683	4	0	0
T6	18941	0	0	0
T16	12450	0	0	0
T17	18769	8	0	0
T18	6982	4	0	0
T19	10547	21	0	0
T20	3300	9	0	0
T21	0	25	0	0
T22	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	109226366	3312	0	0
GateOpen_A	109226366	5060	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109226366	3312	0	0
T1	191203	58	0	0
T2	128932	2	0	0
T3	0	3	0	0
T9	0	22	0	0
T16	1456	0	0	0
T17	2066	1	0	0
T18	763	0	0	0
T19	1151	4	0	0
T20	358	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4818	0	0	0
T66	0	4	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109226366	5060	0	0
T1	191203	62	0	0
T2	128932	6	0	0
T4	694	1	0	0
T5	549	1	0	0
T6	2311	0	0	0
T16	1456	0	0	0
T17	2066	2	0	0
T18	763	1	0	0
T19	1151	5	0	0
T20	358	2	0	0
T21	0	7	0	0
T22	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	218453498	3529	0	0
GateOpen_A	218453498	5277	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453498	3529	0	0
T1	382407	57	0	0
T2	257867	2	0	0
T3	0	4	0	0
T9	0	21	0	0
T16	2913	0	0	0
T17	4131	1	0	0
T18	1525	0	0	0
T19	2302	4	0	0
T20	715	1	0	0
T21	714	6	0	0
T22	1454	0	0	0
T23	9636	0	0	0
T66	0	4	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453498	5277	0	0
T1	382407	61	0	0
T2	257867	6	0	0
T4	1388	1	0	0
T5	1098	1	0	0
T6	4621	0	0	0
T16	2913	0	0	0
T17	4131	2	0	0
T18	1525	1	0	0
T19	2302	5	0	0
T20	715	2	0	0
T21	0	7	0	0
T22	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	438701257	3557	0	0
GateOpen_A	438701257	5306	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438701257	3557	0	0
T1	764386	56	0	0
T2	508697	2	0	0
T3	0	3	0	0
T9	0	21	0	0
T16	5387	0	0	0
T17	8381	1	0	0
T18	3129	0	0	0
T19	4737	4	0	0
T20	1467	1	0	0
T21	1547	6	0	0
T22	2604	0	0	0
T23	16524	0	0	0
T66	0	4	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438701257	5306	0	0
T1	764386	60	0	0
T2	508697	6	0	0
T4	2869	1	0	0
T5	2024	1	0	0
T6	8006	0	0	0
T16	5387	0	0	0
T17	8381	2	0	0
T18	3129	1	0	0
T19	4737	5	0	0
T20	1467	2	0	0
T21	0	7	0	0
T22	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	224771368	3560	0	0
GateOpen_A	224771368	5309	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224771368	3560	0	0
T1	386531	56	0	0
T2	280282	2	0	0
T3	0	4	0	0
T9	0	22	0	0
T16	2694	0	0	0
T17	4191	1	0	0
T18	1565	0	0	0
T19	2357	5	0	0
T20	760	2	0	0
T21	799	3	0	0
T22	1302	0	0	0
T23	8262	0	0	0
T66	0	4	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224771368	5309	0	0
T1	386531	60	0	0
T2	280282	6	0	0
T4	1435	1	0	0
T5	1012	1	0	0
T6	4003	0	0	0
T16	2694	0	0	0
T17	4191	2	0	0
T18	1565	1	0	0
T19	2357	6	0	0
T20	760	3	0	0
T21	0	4	0	0
T22	0	1	0	0